Re: [RFC 1/1 v2] target/riscv: use tcg ops generation to emulate whole reg rvv loads/stores.

[Max Chou]

> +        for (int i = 0; i < size; i += 16) {
> +            addr = get_address(s, rs1, i);
> +            if (is_load) {
> +                tcg_gen_qemu_ld_i128(t16, addr, s->mem_idx,
> +                        MO_LE | MO_128 | atomicity);
> +                tcg_gen_st_i128(t16, tcg_env, vreg_ofs(s, vd) + i);
According to the v spec, the vstart CSR contains the element index on
which the trap was taken.
The vstart CSR will get wrong index if the failed element is not the 
first one
of the element group(ld/st_i128) here.
I create a test case in the following repository for this vstart issue.
https://github.com/rnax/rvv_ldst_test

max