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Re: [PATCH v7 4/6] target/i386: Add couple of feature bits in CPUID_Fn80
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From: |
Dr. David Alan Gilbert |
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Subject: |
Re: [PATCH v7 4/6] target/i386: Add couple of feature bits in CPUID_Fn80000021_EAX |
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Date: |
Mon, 16 Jun 2025 23:33:24 +0000 |
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User-agent: |
Mutt/2.2.12 (2023-09-09) |
* Moger, Babu (babu.moger@amd.com) wrote:
> Hi Dave,
>
> On 6/6/25 07:29, Dr. David Alan Gilbert wrote:
> > * Babu Moger (babu.moger@amd.com) wrote:
> >> Add CPUID bit indicates that a WRMSR to MSR_FS_BASE, MSR_GS_BASE, or
> >> MSR_KERNEL_GS_BASE is non-serializing amd PREFETCHI that the indicates
> >> support for IC prefetch.
> >>
> >> CPUID_Fn80000021_EAX
> >> Bit Feature description
> >> 20 Indicates support for IC prefetch.
> >> 1 FsGsKernelGsBaseNonSerializing.
> >
> > I'm curious about this:
> > a) Is this new CPUs are non-serialising on that write?
> > b) If so, what happens if you run existing kernels/firmware on them?
> > c) Bonus migration question; what happens if you live migrate from a host
> > that claims to be serialising to one that has the extra non-serialising
> > flag but is disabled in the emulated CPU model.
>
> Good question. After looking at the AMD64 Architecture Programmer’s Manual
> again, these writes have always been non-serializing. Behavior has not
> changed.
Ah OK, then nothing to worry about.
> We're just reporting it through CPUID now. This information
> likely isn’t being used anywhere.
Seems curious to add it then!
> Let me know if you have any questions.
No, thanks for the reply.
Dave
> --
> Thanks
> Babu Moger
--
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