Re: [Qemu-ppc] [Qemu-devel] [PATCH 1/2] PPC: Fix interrupt MSR value within the PPC interrupt handler.

[David Gibson]

On Tue, Mar 27, 2012 at 12:47:32PM -0500, Scott Wood wrote:
> On 03/27/2012 10:41 AM, Mark Cave-Ayland wrote:
> > Commit 41557447d30eeb944e42069513df13585f5e6c7f introduced a new method of
> > calculating the MSR for the interrupt context. However this doesn't quite
> > agree with the PowerISA 2.06B specification (pp. 811-814) since too many
> > bits were being cleared.
> > 
> > This patch corrects the calculation of the interrupt MSR whilst including
> > additional comments to clarify which bits are being changed within both the
> > MSR and the interrupt MSR.
> > 
> > Signed-off-by: Mark Cave-Ayland <address@hidden>
> > Signed-off-by: Martin Sucha <address@hidden>
> > ---
> >  target-ppc/helper.c |   23 ++++++++++++++++++++---
> >  1 files changed, 20 insertions(+), 3 deletions(-)
> > 
> > diff --git a/target-ppc/helper.c b/target-ppc/helper.c
> > index 39dcc27..653f818 100644
> > --- a/target-ppc/helper.c
> > +++ b/target-ppc/helper.c
> > @@ -2459,6 +2459,8 @@ static inline void dump_syscall(CPUPPCState *env)
> >  /* Note that this function should be greatly optimized
> >   * when called with a constant excp, from ppc_hw_interrupt
> >   */
> > +#define MSR_BIT(x) ((target_ulong)1 << x)
> 
> If we're going to make this specific to MSRs, might as well cut down on
> the user's verbosity:
> 
> #define MSR_BIT(x) ((target_ulong)1 << MSR_##x)
> 
> ...and move it to a header file.
> 
> Or possibly have the header file define a set of MSRBIT_IR, MSRBIT_DR, etc.
> 
> >  static inline void powerpc_excp(CPUPPCState *env, int excp_model, int excp)
> >  {
> >      target_ulong msr, new_msr, vector;
> > @@ -2478,11 +2480,26 @@ static inline void powerpc_excp(CPUPPCState *env, 
> > int excp_model, int excp)
> >      qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
> >                    " => %08x (%02x)\n", env->nip, excp, env->error_code);
> >  
> > -    /* new srr1 value excluding must-be-zero bits */
> > +    /* new srr1 value with interrupt-specific bits defaulting to zero */
> >      msr = env->msr & ~0x783f0000ULL;
> >  
> > -    /* new interrupt handler msr */
> > -    new_msr = env->msr & ((target_ulong)1 << MSR_ME);
> > +    switch (excp_model) {
> > +    case POWERPC_EXCP_BOOKE:
> > +        /* new interrupt handler msr */
> > +        new_msr = env->msr & ((target_ulong)1 << MSR_ME);
> > +        break;
> > +
> > +    default:
> > +        /* new interrupt handler msr (as per PowerISA 2.06B p.811 and 
> > p.814): 
> > +           1) force the following bits to zero
> > +              IR, DR, FE0, FE1, EE, BE, FP, PMM, PR, SE
> > +           2) default the following bits to zero (can be overidden later 
> > on)
> > +              RI */
> > +        new_msr = env->msr & ~(MSR_BIT(MSR_IR) | MSR_BIT(MSR_DR) 
> > +                      | MSR_BIT(MSR_FE0)| MSR_BIT(MSR_FE1) | 
> > MSR_BIT(MSR_EE) 
> > +                      | MSR_BIT(MSR_BE) | MSR_BIT(MSR_FP) | 
> > MSR_BIT(MSR_PMM) 
> > +                      | MSR_BIT(MSR_PR) | MSR_BIT(MSR_SE) | 
> > MSR_BIT(MSR_RI));
> > +    }
> 
> What about POWERPC_EXCP_40x?  And are all the classic chips OK with the
> 2.06B implementation?

Hrm, yeah.  I think what you ought to do is to use the new logic just
for the "classic" exception models.  Have the default branch remain
the one that just masks ME.  That's wrong, but it's the same wrong as
we have already, and we can fix it later once we've verified what the
right thing to do is for 40x and BookE.

-- 
David Gibson                    | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au  | minimalist, thank you.  NOT _the_ _other_
                                | _way_ _around_!
http://www.ozlabs.org/~dgibson