[Qemu-ppc] [PATCH 0/2 v2] e500: creating CCSR region and registering bar0

[Bharat Bhushan]

From: Bharat Bhushan <address@hidden>

The CCSR memory region is exported to pci device. The MSI interrupt
generation is the main reason to export the CCSR region to PCI device.
This put the requirement to move mpic under CCSR region, but logically
all devices should be under CCSR.
  
So First patch creates the CCSR region and places all emulated devices
under ccsr region.
 
PCI Root complex have TYPE-1 configuration header while PCI endpoint
have type-0 configuration header. The type-1 configuration header have
a BAR (BAR0). In Freescale PCI controller BAR0 is used for mapping pci
address space to CCSR address space.

The second patch maps the BAR0 to ccsr region.

Bharat Bhushan (2):
  e500: Adding CCSR memory region
  Adding BAR0 for e500 PCI controller

 hw/ppc/e500-ccsr.h |   17 +++++++++
 hw/ppc/e500.c      |  100 ++++++++++++++++++++++++++++++++++++++++------------
 hw/ppce500_pci.c   |   30 +++++++++++++++-
 3 files changed, 123 insertions(+), 24 deletions(-)
 create mode 100644 hw/ppc/e500-ccsr.h