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[Qemu-ppc] [PATCH 08/32] target-ppc: Disentangle 64-bit hash MMU get_phy
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PATCH 08/32] target-ppc: Disentangle 64-bit hash MMU get_physical_address() paths |
Date: |
Fri, 15 Feb 2013 19:00:58 +1100 |
Depending on the MSR state, for 64-bit hash MMUs, get_physical_address
can either call check_physical (which has further tests for mmu type)
or get_segment64.
This patch splits off the whole get_physical_addresss() path for 64-bit
hash MMUs into its own function, which handles real mode correctly for
such MMUs without going to check_physical and rechecking the mmu type.
Correspondingly, the 64-bit hash MMU specific path in check_physical() is
removed.
Signed-off-by: David Gibson <address@hidden>
---
target-ppc/cpu.h | 4 ++--
target-ppc/mmu-hash64.c | 19 +++++++++++++++++--
target-ppc/mmu_helper.c | 27 +++++----------------------
3 files changed, 24 insertions(+), 26 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index cf12632..6143142 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1153,8 +1153,8 @@ hwaddr get_pteg_offset(CPUPPCState *env, hwaddr hash, int
pte_size);
void ppc_store_asr (CPUPPCState *env, target_ulong value);
int ppc_store_slb (CPUPPCState *env, target_ulong rb, target_ulong rs);
void dump_slb(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env);
-int get_segment64(CPUPPCState *env, mmu_ctx_t *ctx,
- target_ulong eaddr, int rw, int type);
+int ppc_hash64_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
+ target_ulong eaddr, int rw, int
access_type);
#endif /* defined(TARGET_PPC64) */
#endif /* !defined(CONFIG_USER_ONLY) */
void ppc_store_msr (CPUPPCState *env, target_ulong value);
diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c
index 7b814a1..e6fd148 100644
--- a/target-ppc/mmu-hash64.c
+++ b/target-ppc/mmu-hash64.c
@@ -349,8 +349,8 @@ static int find_pte64(CPUPPCState *env, mmu_ctx_t *ctx, int
h,
return ret;
}
-int get_segment64(CPUPPCState *env, mmu_ctx_t *ctx,
- target_ulong eaddr, int rw, int type)
+static int get_segment64(CPUPPCState *env, mmu_ctx_t *ctx,
+ target_ulong eaddr, int rw, int type)
{
hwaddr hash;
target_ulong vsid;
@@ -434,3 +434,18 @@ int get_segment64(CPUPPCState *env, mmu_ctx_t *ctx,
return ret;
}
+
+int ppc_hash64_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
+ target_ulong eaddr, int rw, int
access_type)
+{
+ bool real_mode = (access_type == ACCESS_CODE && msr_ir == 0)
+ || (access_type != ACCESS_CODE && msr_dr == 0);
+
+ if (real_mode) {
+ ctx->raddr = eaddr & 0x0FFFFFFFFFFFFFFFULL;
+ ctx->prot = PAGE_READ | PAGE_EXEC | PAGE_WRITE;
+ return 0;
+ } else {
+ return get_segment64(env, ctx, eaddr, rw, access_type);
+ }
+}
diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c
index 6950a3f..1f877f9 100644
--- a/target-ppc/mmu_helper.c
+++ b/target-ppc/mmu_helper.c
@@ -1359,15 +1359,7 @@ static inline int check_physical(CPUPPCState *env,
mmu_ctx_t *ctx,
case POWERPC_MMU_BOOKE:
ctx->prot |= PAGE_WRITE;
break;
-#if defined(TARGET_PPC64)
- case POWERPC_MMU_64B:
- case POWERPC_MMU_2_06:
- case POWERPC_MMU_2_06d:
- /* Real address are 60 bits long */
- ctx->raddr &= 0x0FFFFFFFFFFFFFFFULL;
- ctx->prot |= PAGE_WRITE;
- break;
-#endif
+
case POWERPC_MMU_SOFT_4xx_Z:
if (unlikely(msr_pe != 0)) {
/* 403 family add some particular protections,
@@ -1392,15 +1384,10 @@ static inline int check_physical(CPUPPCState *env,
mmu_ctx_t *ctx,
}
}
break;
- case POWERPC_MMU_MPC8xx:
- /* XXX: TODO */
- cpu_abort(env, "MPC8xx MMU model is not implemented\n");
- break;
- case POWERPC_MMU_BOOKE206:
- cpu_abort(env, "BookE 2.06 MMU doesn't have physical real mode\n");
- break;
+
default:
- cpu_abort(env, "Unknown or invalid MMU model\n");
+ /* Caller's checks mean we should never get here for other models */
+ abort();
return -1;
}
@@ -1441,11 +1428,7 @@ static int get_physical_address(CPUPPCState *env,
mmu_ctx_t *ctx,
case POWERPC_MMU_64B:
case POWERPC_MMU_2_06:
case POWERPC_MMU_2_06d:
- if (real_mode) {
- ret = check_physical(env, ctx, eaddr, rw);
- } else {
- ret = get_segment64(env, ctx, eaddr, rw, access_type);
- }
+ ret = ppc_hash64_get_physical_address(env, ctx, eaddr, rw,
access_type);
break;
#endif
--
1.7.10.4
- [Qemu-ppc] [0/32] RFC: 64-bit hash mmu implementation clean up, David Gibson, 2013/02/15
- [Qemu-ppc] [PATCH 01/32] target-ppc: Trivial cleanups in mmu_helper.c, David Gibson, 2013/02/15
- [Qemu-ppc] [PATCH 11/32] target-ppc: Disentangle hash mmu helper functions, David Gibson, 2013/02/15
- [Qemu-ppc] [PATCH 17/32] mmu-hash64: Remove nx from mmu_ctx_hash64, David Gibson, 2013/02/15
- [Qemu-ppc] [PATCH 18/32] mmu-hash64: Remove eaddr field from mmu_ctx_hash64, David Gibson, 2013/02/15
- [Qemu-ppc] [PATCH 04/32] target-ppc: Disentangle 64-bit version of pte_check(), David Gibson, 2013/02/15
- [Qemu-ppc] [PATCH 02/32] target-ppc: Remove address check for logging, David Gibson, 2013/02/15
- [Qemu-ppc] [PATCH 08/32] target-ppc: Disentangle 64-bit hash MMU get_physical_address() paths,
David Gibson <=
- [Qemu-ppc] [PATCH 14/32] mmu-hash64: Add header file for definitions, David Gibson, 2013/02/15
- [Qemu-ppc] [PATCH 12/32] target-ppc: Don't share get_pteg_offset() between 32 and 64-bit, David Gibson, 2013/02/15
- [Qemu-ppc] [PATCH 16/32] mmu-hash64: Stop using access_type, David Gibson, 2013/02/15
- [Qemu-ppc] [PATCH 10/32] target-ppc: Disentangle 64-bit hash version of cpu_get_phys_page_debug(), David Gibson, 2013/02/15
- [Qemu-ppc] [PATCH 19/32] mmu-hash64: Combine ppc_hash64_get_physical_address and get_segment64(), David Gibson, 2013/02/15
- [Qemu-ppc] [PATCH 20/32] mmu-hash64: Cleanup segment-level access checks, David Gibson, 2013/02/15
- [Qemu-ppc] [PATCH 09/32] target-ppc: Disentangle ppc64 hash mmu path for cpu_ppc_handle_mmu_fault, David Gibson, 2013/02/15
- [Qemu-ppc] [PATCH 07/32] target-ppc: Rework get_physical_address(), David Gibson, 2013/02/15
- [Qemu-ppc] [PATCH 05/32] target-ppc: Disentangle 64-bit version of find_pte(), David Gibson, 2013/02/15
- [Qemu-ppc] [PATCH 13/32] target-ppc: mmu_ctx_t should not be a global type, David Gibson, 2013/02/15