the case in qemu where they are based on the 7400 processor.
processors based on it. Therefore, adding the high BATs and the SPRG
4..7 registers, which are e600-specific [1].
on a real MPC8610 target is now able to run on qemu :)
[1]
http://cache.freescale.com/files/32bit/doc/ref_manual/E600CORERM.pdfSigned-off-by: Julio Guerra <
address@hidden>
---
translate_init.c | 119 ++++---------------------------------------------------
1 file changed, 9 insertions(+), 110 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index a8dde96..f038850 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -6292,111 +6292,6 @@ static void init_proc_7457 (CPUPPCState *env)
ppc6xx_irq_init(env);
}
-/* PowerPC e600 */
-#define POWERPC_INSNS_e600 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
- PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
- PPC_FLOAT_STFIWX | \
- PPC_CACHE | PPC_CACHE_ICBI | \
- PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
- PPC_MEM_SYNC | PPC_MEM_EIEIO | \
- PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
- PPC_MEM_TLBIA | PPC_74xx_TLB | \
- PPC_SEGMENT | PPC_EXTERN | \
- PPC_ALTIVEC)
-#define POWERPC_INSNS2_e600 (PPC_NONE)
-#define POWERPC_MSRM_e600 (0x000000000205FF77ULL)
-#define POWERPC_MMU_e600 (POWERPC_MMU_32B)
-#define POWERPC_EXCP_e600 (POWERPC_EXCP_74xx)
-#define POWERPC_INPUT_e600 (PPC_FLAGS_INPUT_6xx)
-#define POWERPC_BFDM_e600 (bfd_mach_ppc_7400)
-#define POWERPC_FLAG_e600 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
- POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
- POWERPC_FLAG_BUS_CLK)
-#define check_pow_e600 check_pow_hid0_74xx
-
-__attribute__ (( unused ))
-static void init_proc_e600 (CPUPPCState *env)
-{
- gen_spr_ne_601(env);
- gen_spr_7xx(env);
- /* Time base */
- gen_tbl(env);
- /* 74xx specific SPR */
- gen_spr_74xx(env);
- /* XXX : not implemented */
- spr_register(env, SPR_UBAMR, "UBAMR",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
- /* LDSTCR */
- /* XXX : not implemented */
- spr_register(env, SPR_LDSTCR, "LDSTCR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* ICTRL */
- /* XXX : not implemented */
- spr_register(env, SPR_ICTRL, "ICTRL",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* MSSSR0 */
- /* XXX : not implemented */
- spr_register(env, SPR_MSSSR0, "MSSSR0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* PMC */
- /* XXX : not implemented */
- spr_register(env, SPR_PMC5, "PMC5",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_UPMC5, "UPMC5",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_PMC6, "PMC6",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_UPMC6, "UPMC6",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
- /* SPRGs */
- spr_register(env, SPR_SPRG4, "SPRG4",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_SPRG5, "SPRG5",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_SPRG6, "SPRG6",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_SPRG7, "SPRG7",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- /* Memory management */
- gen_low_BATs(env);
- gen_high_BATs(env);
- gen_74xx_soft_tlb(env, 128, 2);
- init_excp_7450(env);
- env->dcache_line_size = 32;
- env->icache_line_size = 32;
- /* Allocate hardware IRQ controller */
- ppc6xx_irq_init(env);
-}
-
#if defined (TARGET_PPC64)
/* PowerPC 970 */
#define POWERPC_INSNS_970 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
@@ -7797,7 +7692,9 @@ enum {
POWERPC_SVR_8568E = 0x807D0011 | POWERPC_SVR_E500,
POWERPC_SVR_8572 = 0x80E00010 | POWERPC_SVR_E500,
POWERPC_SVR_8572E = 0x80E80010 | POWERPC_SVR_E500,
- POWERPC_SVR_8610 = 0x80A00011,
+#if 0
+ POWERPC_SVR_8610 = xxx,
+#endif
POWERPC_SVR_8641 = 0x80900021,
POWERPC_SVR_8641D = 0x80900121,
};
@@ -8944,17 +8841,19 @@ static const ppc_def_t ppc_defs[] = {
CPU_POWERPC_MPC8572E, POWERPC_SVR_8572E, e500v2),
/* e600 family */
/* PowerPC e600 core */
- POWERPC_DEF("e600", CPU_POWERPC_e600, e600),
+ POWERPC_DEF("e600", CPU_POWERPC_e600, 7400),
/* PowerPC e600 microcontrollers */
+#if defined (TODO)
/* MPC8610 */
POWERPC_DEF_SVR("MPC8610",
- CPU_POWERPC_MPC8610, POWERPC_SVR_8610, e600),
+ CPU_POWERPC_MPC8610, POWERPC_SVR_8610, 7400),
+#endif
/* MPC8641 */
POWERPC_DEF_SVR("MPC8641",
- CPU_POWERPC_MPC8641, POWERPC_SVR_8641, e600),
+ CPU_POWERPC_MPC8641, POWERPC_SVR_8641, 7400),
/* MPC8641D */
POWERPC_DEF_SVR("MPC8641D",
- CPU_POWERPC_MPC8641D, POWERPC_SVR_8641D, e600),
+ CPU_POWERPC_MPC8641D, POWERPC_SVR_8641D, 7400),
/* 32 bits "classic" PowerPC */
/* PowerPC 6xx family */
/* PowerPC 601 */