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[Qemu-ppc] [PATCH v4 21/29] target-ppc: Enable FSCR facility check for T
From: |
Alexey Kardashevskiy |
Subject: |
[Qemu-ppc] [PATCH v4 21/29] target-ppc: Enable FSCR facility check for TAR |
Date: |
Tue, 3 Jun 2014 19:27:56 +1000 |
This makes user-privileged read/write fail if TAR facility is not enabled
in FSCR.
Since this is the very first check for enabled in FSCR facility,
this also adds gen_fscr_facility_check() for using in spr_write_tar()/
spr_read_tar().
Signed-off-by: Alexey Kardashevskiy <address@hidden>
---
target-ppc/translate_init.c | 29 ++++++++++++++++++++++++++++-
1 file changed, 28 insertions(+), 1 deletion(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 6f0c36b..9b83d56 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7275,6 +7275,21 @@ enum BOOK3S_CPU_TYPE {
BOOK3S_CPU_POWER8
};
+static void gen_fscr_facility_check(void *opaque, int facility_sprn, int bit,
+ int sprn, int cause)
+{
+ TCGv_i32 t1 = tcg_const_i32(bit);
+ TCGv_i32 t2 = tcg_const_i32(sprn);
+ TCGv_i32 t3 = tcg_const_i32(cause);
+
+ gen_update_current_nip(opaque);
+ gen_helper_fscr_facility_check(cpu_env, t1, t2, t3);
+
+ tcg_temp_free_i32(t3);
+ tcg_temp_free_i32(t2);
+ tcg_temp_free_i32(t1);
+}
+
static int check_pow_970 (CPUPPCState *env)
{
if (env->spr[SPR_HID0] & 0x01C00000) {
@@ -7568,10 +7583,22 @@ static void gen_spr_power6_common(CPUPPCState *env)
0x00000000);
}
+static void spr_read_tar(void *opaque, int gprn, int sprn)
+{
+ gen_fscr_facility_check(opaque, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
+ spr_read_generic(opaque, gprn, sprn);
+}
+
+static void spr_write_tar(void *opaque, int sprn, int gprn)
+{
+ gen_fscr_facility_check(opaque, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
+ spr_write_generic(opaque, sprn, gprn);
+}
+
static void gen_spr_power8_tce_address_control(CPUPPCState *env)
{
spr_register(env, SPR_TAR, "TAR",
- &spr_read_generic, &spr_write_generic,
+ &spr_read_tar, &spr_write_tar,
&spr_read_generic, &spr_write_generic,
0x00000000);
}
--
2.0.0
- Re: [Qemu-ppc] [PATCH v4 18/29] target-ppc: Refactor class init for POWER7/8, (continued)
[Qemu-ppc] [PATCH v4 17/29] target-ppc: Switch POWER7/8 classes to use correct PMU SPRs, Alexey Kardashevskiy, 2014/06/03
[Qemu-ppc] [PATCH v4 20/29] target-ppc: Add POWER8's FSCR SPR, Alexey Kardashevskiy, 2014/06/03
[Qemu-ppc] [PATCH v4 13/29] target-ppc: Move POWER8 TCE Address control (TAR) to a helper, Alexey Kardashevskiy, 2014/06/03
[Qemu-ppc] [PATCH v4 16/29] target-ppc: Make use of gen_spr_book3s_lpar() for POWER7/8, Alexey Kardashevskiy, 2014/06/03
[Qemu-ppc] [PATCH v4 21/29] target-ppc: Enable FSCR facility check for TAR,
Alexey Kardashevskiy <=
[Qemu-ppc] [PATCH v4 23/29] target-ppc: Add POWER8's TM SPRs, Alexey Kardashevskiy, 2014/06/03
[Qemu-ppc] [PATCH v4 22/29] target-ppc: Add POWER8's MMCR2/MMCRS SPRs, Alexey Kardashevskiy, 2014/06/03