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Re: [Qemu-ppc] [Qemu-devel] [PULL 075/118] macio: handle non-block ATAPI
From: |
BALATON Zoltan |
Subject: |
Re: [Qemu-ppc] [Qemu-devel] [PULL 075/118] macio: handle non-block ATAPI DMA transfers |
Date: |
Sat, 21 Jun 2014 02:57:51 +0200 (CEST) |
User-agent: |
Alpine 2.02 (LMD 1266 2009-07-14) |
On Fri, 20 Jun 2014, Mark Cave-Ayland wrote:
And also with ATAPI debugging enabled? I suspect the problem is with the
interaction between the DMA/ATAPI systems again.
I forgot that one. I've now rerun with DEBUG_IDE_ATAPI enabled. Here is
with the patch failing:
DBDMA: writel 0x0000000000000d0c <= 0x00e599f0
DBDMA: channel 0x1a reg 0x3
DBDMA: dbdma_cmdptr_load 0x00e599f0
ATAPI limit=0x8000 packet: 43 00 00 00 00 00 00 03 24 00 00 00
DBDMA: DBDMA_run_bh
DBDMA: writel 0x0000000000000d00 <= 0x80008000
DBDMA: channel 0x1a reg 0x0
DBDMA: status 0x00008400
DBDMA: readl 0x0000000000000d00 => 0x80008000
DBDMA: channel 0x1a reg 0x0
DBDMA: DBDMA_run_bh
DBDMA: channel_run
dbdma_cmd 0x7f4cf1325228
req_count 0x0324
command 0x3000
phy_addr 0x00e57d74
cmd_dep 0x00000000
res_count 0x0000
xfer_status 0x0000
DBDMA: start_input
DBDMA: addr 0xe57d74 key 0x0
non-block ATAPI DMA transfer size: 804
io_buffer_size = 0
remainder: 0 io->len: 0 size: 20
end of DMA
done DMA
DBDMA: dbdma_end
DBDMA: conditional_wait
DBDMA: dbdma_cmdptr_save 0x00e599f0
DBDMA: xfer_status 0x00008400 res_count 0x0000
DBDMA: conditional_interrupt
DBDMA: conditional_branch
DBDMA: dbdma_cmdptr_load 0x00e59a00
DBDMA: channel_run
dbdma_cmd 0x7f4cf1325228
req_count 0x0000
command 0x7000
phy_addr 0x00000000
cmd_dep 0x00000000
res_count 0x0000
xfer_status 0x0000
and without the patch when it works:
DBDMA: writel 0x0000000000000d0c <= 0x00e89ce0
DBDMA: channel 0x1a reg 0x3
DBDMA: dbdma_cmdptr_load 0x00e89ce0
ATAPI limit=0x8000 packet: 43 00 00 00 00 00 00 03 24 00 00 00
DBDMA: DBDMA_run_bh
DBDMA: writel 0x0000000000000d00 <= 0x80008000
DBDMA: channel 0x1a reg 0x0
DBDMA: status 0x00008400
DBDMA: readl 0x0000000000000d00 => 0x80008000
DBDMA: channel 0x1a reg 0x0
DBDMA: DBDMA_run_bh
DBDMA: channel_run
dbdma_cmd 0x7fc4dcef2228
req_count 0x0324
command 0x3000
phy_addr 0x00e8ff94
cmd_dep 0x00000000
res_count 0x0000
xfer_status 0x0000
DBDMA: start_input
DBDMA: addr 0xe8ff94 key 0x0
non-block ATAPI DMA transfer size: 20
end of non-block ATAPI DMA transfer
DBDMA: dbdma_end
DBDMA: conditional_wait
DBDMA: dbdma_cmdptr_save 0x00e89ce0
DBDMA: xfer_status 0x00008400 res_count 0x0324
DBDMA: conditional_interrupt
DBDMA: conditional_branch
DBDMA: dbdma_cmdptr_load 0x00e89cf0
DBDMA: channel_run
dbdma_cmd 0x7fc4dcef2228
req_count 0x0000
command 0x7000
phy_addr 0x00000000
cmd_dep 0x00000000
res_count 0x0000
xfer_status 0x0000
DBDMA: readl 0x0000000000000d04 => 0x00008000
DBDMA: channel 0x1a reg 0x1
DBDMA: writel 0x0000000000000d00 <= 0x98000000
DBDMA: channel 0x1a reg 0x0
DBDMA: status 0x00000000
DBDMA: writel 0x0000000000000d0c <= 0x00e89ce0
DBDMA: channel 0x1a reg 0x3
DBDMA: dbdma_cmdptr_load 0x00e89ce0
ATAPI limit=0x8000 packet: 28 00 00 00 00 10 00 00 01 00 00 00
read dma: LBA=16 nb_sectors=1
DBDMA: writel 0x0000000000000d00 <= 0x80008000
DBDMA: channel 0x1a reg 0x0
DBDMA: status 0x00008400
DBDMA: readl 0x0000000000000d00 => 0x80008000
DBDMA: channel 0x1a reg 0x0
DBDMA: DBDMA_run_bh
DBDMA: channel_run
dbdma_cmd 0x7fc4dcef2228
req_count 0x0800
command 0x3000
phy_addr 0x00e7bc20
cmd_dep 0x00000000
res_count 0x0000
xfer_status 0x0000
DBDMA: start_input
DBDMA: addr 0xe7bc20 key 0x0
io_buffer_size = 0
remainder: 0 io->len: 2048 size: 2048
io->len = 0x800
set remainder to: 0
sector_num=64 size=2048, cmd_cmd=0
io_buffer_size = 0x800
remainder: 0 io->len: 0 size: 0
end of transfer
end of DMA
done DMA
DBDMA: dbdma_end
DBDMA: conditional_wait
DBDMA: dbdma_cmdptr_save 0x00e89ce0
DBDMA: xfer_status 0x00008400 res_count 0x0000
DBDMA: conditional_interrupt
DBDMA: conditional_branch
DBDMA: dbdma_cmdptr_load 0x00e89cf0
DBDMA: channel_run
dbdma_cmd 0x7fc4dcef2228
req_count 0x0000
command 0x7000
phy_addr 0x00000000
cmd_dep 0x00000000
res_count 0x0000
xfer_status 0x0000
DBDMA: writel 0x0000000000000d00 <= 0x98000000
DBDMA: channel 0x1a reg 0x0
DBDMA: status 0x00000000
ATAPI limit=0x8000 packet: 00 00 00 00 00 00 00 00 00 00 00 00
DBDMA: writel 0x0000000000000d0c <= 0x00e89ce0
DBDMA: channel 0x1a reg 0x3
DBDMA: dbdma_cmdptr_load 0x00e89ce0
ATAPI limit=0x8000 packet: 43 00 00 00 00 00 00 03 24 00 00 00
DBDMA: writel 0x0000000000000d00 <= 0x80008000
DBDMA: channel 0x1a reg 0x0
DBDMA: status 0x00008400
DBDMA: readl 0x0000000000000d00 => 0x80008000
DBDMA: channel 0x1a reg 0x0
DBDMA: DBDMA_run_bh
DBDMA: channel_run
dbdma_cmd 0x7fc4dcef2228
req_count 0x0324
command 0x3000
phy_addr 0x00e98dd4
cmd_dep 0x00000000
res_count 0x0000
xfer_status 0x0000
DBDMA: start_input
DBDMA: addr 0xe98dd4 key 0x0
non-block ATAPI DMA transfer size: 20
end of non-block ATAPI DMA transfer
DBDMA: dbdma_end
DBDMA: conditional_wait
DBDMA: dbdma_cmdptr_save 0x00e89ce0
DBDMA: xfer_status 0x00008400 res_count 0x0324
DBDMA: conditional_interrupt
DBDMA: conditional_branch
DBDMA: dbdma_cmdptr_load 0x00e89cf0
DBDMA: channel_run
dbdma_cmd 0x7fc4dcef2228
req_count 0x0000
command 0x7000
phy_addr 0x00000000
cmd_dep 0x00000000
res_count 0x0000
xfer_status 0x0000
DBDMA: writel 0x0000000000000d00 <= 0x98000000
DBDMA: channel 0x1a reg 0x0
DBDMA: status 0x00000000
DBDMA: writel 0x0000000000000d0c <= 0x00e89ce0
DBDMA: channel 0x1a reg 0x3
DBDMA: dbdma_cmdptr_load 0x00e89ce0
ATAPI limit=0x8000 packet: 28 00 00 00 00 10 00 00 01 00 00 00
read dma: LBA=16 nb_sectors=1
The only difference in the common part I can see is the different transfer
size.
I'm afraid as you're the only person that can boot MorphOS this far then we
need you to diagnose and suggest a suitable alternative by comparing the
before and after output. Since MacOS is already a supported client then if no
solution can be found then it is likely that this patch will be reverted :(
Unfortunately I can't make sense of the mess in macio.c so I cannot
suggest a solution as I don't understand what's happening and how should
it work. I can help in testing and trying things you tell me to do but I
cannot solve it by myself. (It would probably help if the unaligned hacks
could be removed if this is already possible with the current block layer
as that should simplify the code so it could be understood. I can't do
that either though as I don't know what needs to be done for this.)
I wish more people could boot MorphOS by now but that still needs the
patches I've sent for OpenBIOS and QEMU that are not merged yet and
there's also the problem with the MMU exceptions that we don't have a
solution for yet.
Regards,
BALATON Zoltan
- [Qemu-ppc] [PULL 073/118] spapr: Add support for time base offset migration, (continued)
- [Qemu-ppc] [PULL 073/118] spapr: Add support for time base offset migration, Alexander Graf, 2014/06/04
- [Qemu-ppc] [PULL 027/118] target-ppc: Introduce Generator Macros for DFP Arithmetic Forms, Alexander Graf, 2014/06/04
- [Qemu-ppc] [PULL 061/118] PPC: e500: implement PCI INTx routing, Alexander Graf, 2014/06/04
- [Qemu-ppc] [PULL 064/118] PPC: Make all e500 CPUs SVR aware, Alexander Graf, 2014/06/04
- [Qemu-ppc] [PULL 050/118] target-ppc: Introduce DFP Insert Biased Exponent, Alexander Graf, 2014/06/04
- [Qemu-ppc] [PULL 058/118] target-ppc: Refactor AES Instructions, Alexander Graf, 2014/06/04
- [Qemu-ppc] [PULL 075/118] macio: handle non-block ATAPI DMA transfers, Alexander Graf, 2014/06/04
- Re: [Qemu-ppc] [PULL 075/118] macio: handle non-block ATAPI DMA transfers, Mark Cave-Ayland, 2014/06/20
- Re: [Qemu-ppc] [PULL 075/118] macio: handle non-block ATAPI DMA transfers, BALATON Zoltan, 2014/06/20
- Re: [Qemu-ppc] [Qemu-devel] [PULL 075/118] macio: handle non-block ATAPI DMA transfers, Mark Cave-Ayland, 2014/06/20
- Re: [Qemu-ppc] [Qemu-devel] [PULL 075/118] macio: handle non-block ATAPI DMA transfers,
BALATON Zoltan <=
- Re: [Qemu-ppc] [Qemu-devel] [PULL 075/118] macio: handle non-block ATAPI DMA transfers, Alexander Graf, 2014/06/23
- Re: [Qemu-ppc] [Qemu-devel] [PULL 075/118] macio: handle non-block ATAPI DMA transfers, BALATON Zoltan, 2014/06/23
- Re: [Qemu-ppc] [Qemu-devel] [PULL 075/118] macio: handle non-block ATAPI DMA transfers, Mark Cave-Ayland, 2014/06/23
- Re: [Qemu-ppc] [Qemu-devel] [PULL 075/118] macio: handle non-block ATAPI DMA transfers, Kevin Wolf, 2014/06/24
- Re: [Qemu-ppc] [Qemu-devel] [PULL 075/118] macio: handle non-block ATAPI DMA transfers, BALATON Zoltan, 2014/06/24
- Re: [Qemu-ppc] [Qemu-devel] [PULL 075/118] macio: handle non-block ATAPI DMA transfers, Alexander Graf, 2014/06/24
- Re: [Qemu-ppc] [Qemu-devel] [PULL 075/118] macio: handle non-block ATAPI DMA transfers, Kevin Wolf, 2014/06/24
- Re: [Qemu-ppc] [Qemu-devel] [PULL 075/118] macio: handle non-block ATAPI DMA transfers, Alexander Graf, 2014/06/24
- Re: [Qemu-ppc] [Qemu-devel] [PULL 075/118] macio: handle non-block ATAPI DMA transfers, Kevin Wolf, 2014/06/24
- Re: [Qemu-ppc] [Qemu-devel] [PULL 075/118] macio: handle non-block ATAPI DMA transfers, Alexander Graf, 2014/06/24