Re: [Qemu-ppc] [RFC PATCH 3/4] ppc: Use split I/D mmu modes to avoid flushes on interrupts

[Paolo Bonzini]

On 19/07/2015 00:20, Benjamin Herrenschmidt wrote:
> +     * For BookE, we need in theory 8 MMU modes, which would
> +     * reduce performance, so instead, we ignore msr_hv and
> +     * will flush on HV context switches. We *could* improve
> +     * things a bit if needed by using 4 and 5 as HV and flush
> +     * only when HV mode changes AS but that complicates things
> +     * as we would need to remember which is the current AS mode
> +     * for HV for I and D and split more would be hell.
> +     *

8 MMU modes wouldn't reduce performance, only 9 would:

#define CPU_TLB_BITS                                             \
    MIN(8,                                                       \
        TCG_TARGET_TLB_DISPLACEMENT_BITS - CPU_TLB_ENTRY_BITS -  \
        (NB_MMU_MODES <= 1 ? 0 :                                 \
         NB_MMU_MODES <= 2 ? 1 :                                 \
         NB_MMU_MODES <= 4 ? 2 :                                 \
         NB_MMU_MODES <= 8 ? 3 : 4))

Paolo