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Re: [Qemu-ppc] [PATCH 11/77] ppc: Create cpu_ppc_set_papr() helper
From: |
David Gibson |
Subject: |
Re: [Qemu-ppc] [PATCH 11/77] ppc: Create cpu_ppc_set_papr() helper |
Date: |
Mon, 16 Nov 2015 16:30:13 +1100 |
User-agent: |
Mutt/1.5.23 (2015-06-09) |
On Wed, Nov 11, 2015 at 11:27:24AM +1100, Benjamin Herrenschmidt wrote:
> And move the code adjusting the MSR mask and calling kvmppc_set_papr()
> to it. This allows us to add a few more things such as disabling setting
> of MSR:HV and appropriate LPCR bits which will be used when fixing
> the exception model.
>
> Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Reviewed-by: David Gibson <address@hidden>
> ---
> hw/ppc/spapr.c | 12 +++---------
> target-ppc/cpu.h | 1 +
> target-ppc/translate_init.c | 37 ++++++++++++++++++++++++++++++++++++-
> 3 files changed, 40 insertions(+), 10 deletions(-)
>
> diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
> index 37d071e..610629e 100644
> --- a/hw/ppc/spapr.c
> +++ b/hw/ppc/spapr.c
> @@ -1606,15 +1606,8 @@ static void spapr_cpu_init(sPAPRMachineState *spapr,
> PowerPCCPU *cpu)
> /* Set time-base frequency to 512 MHz */
> cpu_ppc_tb_init(env, TIMEBASE_FREQ);
>
> - /* PAPR always has exception vectors in RAM not ROM. To ensure this,
> - * MSR[IP] should never be set.
> - */
> - env->msr_mask &= ~(1 << 6);
> -
> - /* Tell KVM that we're in PAPR mode */
> - if (kvm_enabled()) {
> - kvmppc_set_papr(cpu);
> - }
> + /* Enable PAPR mode in TCG or KVM */
> + cpu_ppc_set_papr(cpu);
>
> if (cpu->max_compat) {
> if (ppc_set_compat(cpu, cpu->max_compat) < 0) {
> @@ -1791,6 +1784,7 @@ static void ppc_spapr_init(MachineState *machine)
> fprintf(stderr, "Unable to find PowerPC CPU definition\n");
> exit(1);
> }
> +
> spapr_cpu_init(spapr, cpu);
> }
>
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index 611367f..357b6e7 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -1229,6 +1229,7 @@ void store_booke_tcr (CPUPPCState *env, target_ulong
> val);
> void store_booke_tsr (CPUPPCState *env, target_ulong val);
> void ppc_tlb_invalidate_all (CPUPPCState *env);
> void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
> +void cpu_ppc_set_papr(PowerPCCPU *cpu);
> #endif
> #endif
>
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index 1d402e1..7bcfbc0 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -8423,8 +8423,43 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
> pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
> pcc->threads_per_core = 8;
> }
> -#endif /* defined (TARGET_PPC64) */
>
> +#if !defined(CONFIG_USER_ONLY)
> +
> +void cpu_ppc_set_papr(PowerPCCPU *cpu)
> +{
> + CPUPPCState *env = &cpu->env;
> + ppc_spr_t *lpcr = &env->spr_cb[SPR_LPCR];
> +
> + /* PAPR always has exception vectors in RAM not ROM. To ensure this,
> + * MSR[IP] should never be set.
> + *
> + * We also disallow setting of MSR_HV
> + */
> + env->msr_mask &= ~((1ull << MSR_EP) | MSR_HVB);
> +
> + /* Set emulated LPCR to not send interrupts to hypervisor. Note that
> + * under KVM, the actual HW LPCR will be set differently by KVM itself,
> + * the settings below ensure proper operations with TCG in absence of
> + * a real hypervisor
> + */
> + lpcr->default_value &= ~(LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV);
> + lpcr->default_value |= LPCR_LPES0 | LPCR_LPES1;
> +
> + /* We should be followed by a CPU reset but update the active value
> + * just in case...
> + */
> + env->spr[SPR_LPCR] = lpcr->default_value;
> +
> + /* Tell KVM that we're in PAPR mode */
> + if (kvm_enabled()) {
> + kvmppc_set_papr(cpu);
> + }
> +}
> +
> +#endif /* !defined(CONFIG_USER_ONLY) */
> +
> +#endif /* defined (TARGET_PPC64) */
>
>
> /*****************************************************************************/
> /* Generic CPU instantiation routine
> */
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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- Re: [Qemu-ppc] [PATCH 07/77] ppc: Add a bunch of hypervisor SPRs to Book3s, (continued)
- [Qemu-ppc] [PATCH 05/77] ppc: Update SPR definitions, Benjamin Herrenschmidt, 2015/11/10
- [Qemu-ppc] [PATCH 11/77] ppc: Create cpu_ppc_set_papr() helper, Benjamin Herrenschmidt, 2015/11/10
- Re: [Qemu-ppc] [PATCH 11/77] ppc: Create cpu_ppc_set_papr() helper,
David Gibson <=
- [Qemu-ppc] [PATCH 12/77] ppc: Better figure out if processor has HV mode, Benjamin Herrenschmidt, 2015/11/10
- [Qemu-ppc] [PATCH 09/77] ppc: Fix do_rfi() for rfi emulation, Benjamin Herrenschmidt, 2015/11/10
[Qemu-ppc] [PATCH 08/77] ppc: Add number of threads per core to the processor definition, Benjamin Herrenschmidt, 2015/11/10
[Qemu-ppc] [PATCH 03/77] ppc: Do some batching of TCG tlb flushes, Benjamin Herrenschmidt, 2015/11/10