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Re: [Qemu-ppc] [Qemu-devel] [PATCH v3 10/10] ppc: A couple more dummy PO
From: |
Thomas Huth |
Subject: |
Re: [Qemu-ppc] [Qemu-devel] [PATCH v3 10/10] ppc: A couple more dummy POWER8 Book4 regs |
Date: |
Tue, 22 Mar 2016 14:56:25 +0100 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.6.0 |
On 21.03.2016 13:52, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt <address@hidden>
>
> Signed-off-by: Benjamin Herrenschmidt <address@hidden>
> [clg: squashed in patch 'ppc: Add dummy ACOP SPR' ]
> Signed-off-by: Cédric Le Goater <address@hidden>
> Reviewed-by: Thomas Huth <address@hidden>
> Reviewed-by: David Gibson <address@hidden>
> ---
> target-ppc/cpu.h | 3 +++
> target-ppc/translate_init.c | 12 ++++++++++++
> 2 files changed, 15 insertions(+)
>
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index 29c48600d950..676081e69dc0 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -1355,7 +1355,9 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool
> ifetch)
> #define SPR_SRR1 (0x01B)
> #define SPR_CFAR (0x01C)
> #define SPR_AMR (0x01D)
> +#define SPR_ACOP (0x01F)
> #define SPR_BOOKE_PID (0x030)
> +#define SPR_BOOKS_PID (0x030)
> #define SPR_BOOKE_DECAR (0x036)
> #define SPR_BOOKE_CSRR0 (0x03A)
> #define SPR_BOOKE_CSRR1 (0x03B)
> @@ -1706,6 +1708,7 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool
> ifetch)
> #define SPR_POWER_SPMC1 (0x37C)
> #define SPR_POWER_SPMC2 (0x37D)
> #define SPR_POWER_MMCRS (0x37E)
> +#define SPR_WORT (0x37F)
> #define SPR_PPR (0x380)
> #define SPR_750_GQR0 (0x390)
> #define SPR_440_DNV0 (0x390)
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index 5f53098faef7..51e8058c468e 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -8018,6 +8018,18 @@ static void gen_spr_power8_ic(CPUPPCState *env)
> &spr_read_generic, SPR_NOACCESS,
> &spr_read_generic, &spr_write_generic,
> 0);
> + spr_register_kvm(env, SPR_ACOP, "ACOP",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + KVM_REG_PPC_ACOP, 0);
> + spr_register_kvm(env, SPR_BOOKS_PID, "PID",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + KVM_REG_PPC_PID, 0);
> + spr_register_kvm(env, SPR_WORT, "WORT",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + KVM_REG_PPC_WORT, 0);
> #endif
> }
In the original patch, the registers had been added to a function called
gen_spr_power8_book4() ... now they are added to gen_spr_power8_ic() ...
was that on purpose or rather by accident?
Thomas
- [Qemu-ppc] [PATCH v3 05/10] ppc: Add dummy SPR_IC for POWER8, (continued)
- [Qemu-ppc] [PATCH v3 05/10] ppc: Add dummy SPR_IC for POWER8, Cédric Le Goater, 2016/03/21
- [Qemu-ppc] [PATCH v3 01/10] ppc: Update SPR definitions, Cédric Le Goater, 2016/03/21
- [Qemu-ppc] [PATCH v3 06/10] ppc: Initialize AMOR in PAPR mode, Cédric Le Goater, 2016/03/21
- [Qemu-ppc] [PATCH v3 03/10] ppc: Add a bunch of hypervisor SPRs to Book3s, Cédric Le Goater, 2016/03/21
- [Qemu-ppc] [PATCH v3 04/10] ppc: Create cpu_ppc_set_papr() helper, Cédric Le Goater, 2016/03/21
- [Qemu-ppc] [PATCH v3 07/10] ppc: Fix writing to AMR/UAMOR, Cédric Le Goater, 2016/03/21
- [Qemu-ppc] [PATCH v3 08/10] ppc: Add POWER8 IAMR register, Cédric Le Goater, 2016/03/21
- [Qemu-ppc] [PATCH v3 10/10] ppc: A couple more dummy POWER8 Book4 regs, Cédric Le Goater, 2016/03/21
- Re: [Qemu-ppc] [Qemu-devel] [PATCH v3 10/10] ppc: A couple more dummy POWER8 Book4 regs,
Thomas Huth <=
- [Qemu-ppc] [PATCH v3 09/10] ppc: Add dummy CIABR SPR, Cédric Le Goater, 2016/03/21
- Re: [Qemu-ppc] [PATCH v3 00/10] ppc: preparing pnv landing, David Gibson, 2016/03/21