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[Qemu-ppc] [PATCH 11/12] ppc: Get out of emulation on SMT "OR" ops
From: |
Cédric Le Goater |
Subject: |
[Qemu-ppc] [PATCH 11/12] ppc: Get out of emulation on SMT "OR" ops |
Date: |
Tue, 3 May 2016 18:03:33 +0200 |
From: Benjamin Herrenschmidt <address@hidden>
Otherwise tight loops at smt_low for example, which OPAL does,
eat so much CPU that we can't boot a kernel anymore. With that,
I can boot 8 CPUs just fine with powernv.
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Reviewed-by: David Gibson <address@hidden>
---
target-ppc/translate.c | 21 ++++++++++++++++++---
1 file changed, 18 insertions(+), 3 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 3fe08e0920d8..875862db33ee 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -1398,6 +1398,19 @@ GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
/* nor & nor. */
GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
+#if defined(TARGET_PPC64)
+static void gen_pause(DisasContext *ctx)
+{
+ TCGv_i32 t0 = tcg_const_i32(0);
+ tcg_gen_st_i32(t0, cpu_env,
+ -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
+ tcg_temp_free_i32(t0);
+
+ /* Stop translation, this gives other CPUs a chance to run */
+ gen_exception_err(ctx, EXCP_HLT, 1);
+}
+#endif /* defined(TARGET_PPC64) */
+
/* or & or. */
static void gen_or(DisasContext *ctx)
{
@@ -1453,7 +1466,7 @@ static void gen_or(DisasContext *ctx)
}
break;
case 7:
- if (ctx->hv) {
+ if (ctx->hv && !ctx->pr) {
/* Set process priority to very high */
prio = 7;
}
@@ -1470,6 +1483,10 @@ static void gen_or(DisasContext *ctx)
tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
gen_store_spr(SPR_PPR, t0);
tcg_temp_free(t0);
+ /* Pause us out of TCG otherwise spin loops with smt_low
+ * eat too much CPU and the kernel hangs
+ */
+ gen_pause(ctx);
}
#endif
}
@@ -1495,8 +1512,6 @@ static void gen_ori(DisasContext *ctx)
target_ulong uimm = UIMM(ctx->opcode);
if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
- /* NOP */
- /* XXX: should handle special NOPs for POWER series */
return;
}
tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
--
2.1.4
- Re: [Qemu-ppc] [PATCH 07/12] ppc: Better figure out if processor has HV mode, (continued)
[Qemu-ppc] [PATCH 04/12] ppc: Add a bunch of hypervisor SPRs to Book3s, Cédric Le Goater, 2016/05/03
[Qemu-ppc] [PATCH 12/12] ppc: Add PPC_64H instruction flag to POWER7 and POWER8, Cédric Le Goater, 2016/05/03
[Qemu-ppc] [PATCH 01/12] ppc: Remove MMU_MODEn_SUFFIX definitions, Cédric Le Goater, 2016/05/03
[Qemu-ppc] [PATCH 09/12] ppc: Change 'invalid' bit mask of tlbiel and tlbie, Cédric Le Goater, 2016/05/03
[Qemu-ppc] [PATCH 11/12] ppc: Get out of emulation on SMT "OR" ops,
Cédric Le Goater <=
[Qemu-ppc] [PATCH 08/12] ppc: tlbie, tlbia and tlbisync are HV only, Cédric Le Goater, 2016/05/03
Re: [Qemu-ppc] [PATCH 00/12] ppc: preparing pnv landing (round 2), David Gibson, 2016/05/26