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[Qemu-ppc] [RFC v1 09/13] target-ppc: add cmpeqb instruction
From: |
Nikunj A Dadhania |
Subject: |
[Qemu-ppc] [RFC v1 09/13] target-ppc: add cmpeqb instruction |
Date: |
Mon, 18 Jul 2016 22:35:13 +0530 |
From: Swapnil Bokade <address@hidden>
Search a byte in the stream of 8bytes provided in the register
Signed-off-by: Sandipan Das <address@hidden>
[ Modified the logic to use lesser temporaries ]
Signed-off-by: Nikunj A Dadhania <address@hidden>
---
target-ppc/translate.c | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index a57f7dd..8f7ff49 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -856,6 +856,32 @@ static void gen_cmprb(DisasContext *ctx)
tcg_temp_free(src2hi);
}
+/* cmpeqb */
+static void gen_cmpeqb(DisasContext *ctx)
+{
+ TCGLabel *l1 = gen_new_label();
+ TCGLabel *l2 = gen_new_label();
+ TCGv src1 = tcg_temp_local_new();
+ TCGv t0 = tcg_temp_local_new();
+ TCGv arg1 = cpu_gpr[rB(ctx->opcode)];
+ int i;
+
+ tcg_gen_andi_tl(src1, cpu_gpr[rA(ctx->opcode)], 0xFF);
+ for (i = 0; i < 64; i += 8) {
+ tcg_gen_shri_tl(t0, arg1, i);
+ tcg_gen_andi_tl(t0, t0, 0xFF);
+ tcg_gen_brcond_tl(TCG_COND_EQ, src1, t0, l1);
+ }
+ tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0);
+ tcg_gen_br(l2);
+ gen_set_label(l1);
+ /* Set match bit, i.e. CRF_GT */
+ tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 1 << CRF_GT);
+ gen_set_label(l2);
+ tcg_temp_free(src1);
+ tcg_temp_free(t0);
+}
+
/* isel (PowerPC 2.03 specification) */
static void gen_isel(DisasContext *ctx)
{
@@ -10040,6 +10066,7 @@ GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000,
PPC_INTEGER),
GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
+GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300),
GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
--
2.7.4
- [Qemu-ppc] [RFC v1 08/13] target-ppc: add cnttzw[.] instruction, (continued)
- [Qemu-ppc] [RFC v1 08/13] target-ppc: add cnttzw[.] instruction, Nikunj A Dadhania, 2016/07/18
- [Qemu-ppc] [RFC v1 10/13] target-ppc: add setb instruction, Nikunj A Dadhania, 2016/07/18
- [Qemu-ppc] [RFC v1 11/13] target-ppc: add maddld instruction, Nikunj A Dadhania, 2016/07/18
- [Qemu-ppc] [RFC v1 09/13] target-ppc: add cmpeqb instruction,
Nikunj A Dadhania <=
- Re: [Qemu-ppc] [RFC v1 09/13] target-ppc: add cmpeqb instruction, Nikunj A Dadhania, 2016/07/18
- Re: [Qemu-ppc] [Qemu-devel] [RFC v1 09/13] target-ppc: add cmpeqb instruction, Richard Henderson, 2016/07/21
- Re: [Qemu-ppc] [Qemu-devel] [RFC v1 09/13] target-ppc: add cmpeqb instruction, Nikunj A Dadhania, 2016/07/21
- Re: [Qemu-ppc] [Qemu-devel] [RFC v1 09/13] target-ppc: add cmpeqb instruction, Nikunj A Dadhania, 2016/07/22
- Re: [Qemu-ppc] [Qemu-devel] [RFC v1 09/13] target-ppc: add cmpeqb instruction, Richard Henderson, 2016/07/22
- Re: [Qemu-ppc] [Qemu-devel] [RFC v1 09/13] target-ppc: add cmpeqb instruction, Nikunj A Dadhania, 2016/07/23
- Re: [Qemu-ppc] [Qemu-devel] [RFC v1 09/13] target-ppc: add cmpeqb instruction, Richard Henderson, 2016/07/23
Re: [Qemu-ppc] [RFC v1 09/13] target-ppc: add cmpeqb instruction, David Gibson, 2016/07/22
[Qemu-ppc] [RFC v1 12/13] target-ppc: add maddhd and maddhdu instruction, Nikunj A Dadhania, 2016/07/18