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Re: [Qemu-ppc] [PATCH RFC v0 3/6] target-ppc: add vcmpnez[b, h, w][.] in
From: |
David Gibson |
Subject: |
Re: [Qemu-ppc] [PATCH RFC v0 3/6] target-ppc: add vcmpnez[b, h, w][.] instructions |
Date: |
Wed, 27 Jul 2016 15:57:43 +1000 |
User-agent: |
Mutt/1.6.2 (2016-07-01) |
On Wed, Jul 27, 2016 at 12:56:55AM +0530, Nikunj A Dadhania wrote:
> From: Swapnil Bokade <address@hidden>
>
> Adds following instructions:
>
> vcmpnezb[.]: Vector Compare Not Equal or Zero Byte
> vcmpnezh[.]: Vector Compare Not Equal or Zero Halfword
> vcmpnezw[.]: Vector Compare Not Equal or Zero Word
>
> Signed-off-by: Swapnil Bokade <address@hidden>
> Signed-off-by: Nikunj A Dadhania <address@hidden>
> ---
> target-ppc/helper.h | 6 ++++++
> target-ppc/int_helper.c | 49
> +++++++++++++++++++++++++++++++++++++++++++++++++
> target-ppc/translate.c | 6 ++++++
> 3 files changed, 61 insertions(+)
>
> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
> index ff6287e..e93b84b 100644
> --- a/target-ppc/helper.h
> +++ b/target-ppc/helper.h
> @@ -144,6 +144,9 @@ DEF_HELPER_4(vcmpequb, void, env, avr, avr, avr)
> DEF_HELPER_4(vcmpequh, void, env, avr, avr, avr)
> DEF_HELPER_4(vcmpequw, void, env, avr, avr, avr)
> DEF_HELPER_4(vcmpequd, void, env, avr, avr, avr)
> +DEF_HELPER_4(vcmpnezb, void, env, avr, avr, avr)
> +DEF_HELPER_4(vcmpnezh, void, env, avr, avr, avr)
> +DEF_HELPER_4(vcmpnezw, void, env, avr, avr, avr)
> DEF_HELPER_4(vcmpgtub, void, env, avr, avr, avr)
> DEF_HELPER_4(vcmpgtuh, void, env, avr, avr, avr)
> DEF_HELPER_4(vcmpgtuw, void, env, avr, avr, avr)
> @@ -160,6 +163,9 @@ DEF_HELPER_4(vcmpequb_dot, void, env, avr, avr, avr)
> DEF_HELPER_4(vcmpequh_dot, void, env, avr, avr, avr)
> DEF_HELPER_4(vcmpequw_dot, void, env, avr, avr, avr)
> DEF_HELPER_4(vcmpequd_dot, void, env, avr, avr, avr)
> +DEF_HELPER_4(vcmpnezb_dot, void, env, avr, avr, avr)
> +DEF_HELPER_4(vcmpnezh_dot, void, env, avr, avr, avr)
> +DEF_HELPER_4(vcmpnezw_dot, void, env, avr, avr, avr)
> DEF_HELPER_4(vcmpgtub_dot, void, env, avr, avr, avr)
> DEF_HELPER_4(vcmpgtuh_dot, void, env, avr, avr, avr)
> DEF_HELPER_4(vcmpgtuw_dot, void, env, avr, avr, avr)
> diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
> index c1b341c..bffe8d6 100644
> --- a/target-ppc/int_helper.c
> +++ b/target-ppc/int_helper.c
> @@ -718,6 +718,55 @@ VCMP(gtsd, >, s64)
> #undef VCMP_DO
> #undef VCMP
>
> +#define VCMPNEZ_DO(suffix, element, record) \
> +void helper_vcmpnez##suffix(CPUPPCState *env, ppc_avr_t *r, \
> + ppc_avr_t *a, ppc_avr_t *b) \
> +{ \
> + uint64_t ones = (uint64_t)-1; \
> + uint64_t all = ones; \
> + uint64_t none = 0; \
> + int i; \
> + \
> + for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
> + uint64_t result = ((a->element[i] == 0) \
> + || (b->element[i] == 0) \
> + || (a->element[i] != b->element[i]) ? \
> + ones : 0x0);
> \
Couldn't you just use r->element[i] = result instead of the switch?
> + switch (sizeof(a->element[0])) { \
> + case 8: \
> + r->u64[i] = result; \
> + break;
> \
Also it doesn't actually look like there is a 64-bit case.
> + case 4: \
> + r->u32[i] = result; \
> + break; \
> + case 2: \
> + r->u16[i] = result; \
> + break; \
> + case 1: \
> + r->u8[i] = result; \
> + break; \
> + } \
> + all &= result; \
> + none |= result; \
> + } \
> + if (record) { \
> + env->crf[6] = ((all != 0) << 3) | ((none == 0) << 1); \
> + } \
> +}
> +
> +/* VCMPNEZ - Vector compare not equal to zero
> + * suffix - instruction mnemonic suffix (b: byte, h: halfword, w: word)
> + * element - element type to access from vector
> + */
> +#define VCMPNEZ(suffix, element) \
> + VCMPNEZ_DO(suffix, element, 0) \
> + VCMPNEZ_DO(suffix##_dot, element, 1)
> +VCMPNEZ(b, u8)
> +VCMPNEZ(h, u16)
> +VCMPNEZ(w, u32)
> +#undef VCMPNEZ_DO
> +#undef VCMPNEZ
> +
> #define VCMPFP_DO(suffix, compare, order, record) \
> void helper_vcmp##suffix(CPUPPCState *env, ppc_avr_t *r, \
> ppc_avr_t *a, ppc_avr_t *b) \
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index b18e13f..7cf0c8e 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -7565,6 +7565,9 @@ GEN_VXRFORM(vcmpequb, 3, 0)
> GEN_VXRFORM(vcmpequh, 3, 1)
> GEN_VXRFORM(vcmpequw, 3, 2)
> GEN_VXRFORM(vcmpequd, 3, 3)
> +GEN_VXRFORM(vcmpnezb, 3, 4)
> +GEN_VXRFORM(vcmpnezh, 3, 5)
> +GEN_VXRFORM(vcmpnezw, 3, 6)
> GEN_VXRFORM(vcmpgtsb, 3, 12)
> GEN_VXRFORM(vcmpgtsh, 3, 13)
> GEN_VXRFORM(vcmpgtsw, 3, 14)
> @@ -10998,6 +11001,9 @@ GEN_VXFORM(vminfp, 5, 17),
> GEN_VXRFORM(vcmpequb, 3, 0)
> GEN_VXRFORM(vcmpequh, 3, 1)
> GEN_VXRFORM(vcmpequw, 3, 2)
> +GEN_VXRFORM(vcmpnezb, 3, 4)
> +GEN_VXRFORM(vcmpnezh, 3, 5)
> +GEN_VXRFORM(vcmpnezw, 3, 6)
> GEN_VXRFORM(vcmpgtsb, 3, 12)
> GEN_VXRFORM(vcmpgtsh, 3, 13)
> GEN_VXRFORM(vcmpgtsw, 3, 14)
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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- [Qemu-ppc] [PATCH RFC v0 0/6] POWER9 TCG enablements - part2, Nikunj A Dadhania, 2016/07/26
- [Qemu-ppc] [PATCH RFC v0 1/6] target-ppc: add dtstsfi[q] instructions, Nikunj A Dadhania, 2016/07/26
- [Qemu-ppc] [PATCH RFC v0 2/6] target-ppc: add vabsdu[b, h, w] instructions, Nikunj A Dadhania, 2016/07/26
- [Qemu-ppc] [PATCH RFC v0 3/6] target-ppc: add vcmpnez[b, h, w][.] instructions, Nikunj A Dadhania, 2016/07/26
- Re: [Qemu-ppc] [PATCH RFC v0 3/6] target-ppc: add vcmpnez[b, h, w][.] instructions,
David Gibson <=
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- [Qemu-ppc] [PATCH RFC v0 5/6] target-ppc: add vsrv instruction, Nikunj A Dadhania, 2016/07/26
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