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Re: [Qemu-ppc] [PATCH v4 0/9] POWER9 TCG enablements - part4
From: |
Thomas Huth |
Subject: |
Re: [Qemu-ppc] [PATCH v4 0/9] POWER9 TCG enablements - part4 |
Date: |
Wed, 28 Sep 2016 11:28:26 +0200 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.3.0 |
On 28.09.2016 07:31, Nikunj A Dadhania wrote:
> This series contains 7 new instructions for POWER9 ISA3.0
> Use newer qemu load/store tcg helpers and optimize stxvw4x and lxvw4x.
>
> GCC was adding epilogue for every VSX instructions causing change in
> behaviour. For testing the load vector instructions used mfvsrld/mfvsrd
> for loading vsr to register. And for testing store vector, used mtvsrdd
> instructions. This helped in getting rid of the epilogue added by gcc. Tried
> adding the test cases to kvm-unit-tests, but executing vsx instructions
> results in cpu exception. Will debug that later. I will send the test code
> and steps to execute as reply to this email.
Did you enable the VEC bit in the MSR before trying to run your
instruction in a kvm-unit-test? If not, that might be the cause.
Alternatively, there is also a tests/tcg/ folder in QEMU ... you could
add a tests/tcg/ppc64 subfolder there.
Thomas
- Re: [Qemu-ppc] [PATCH v4 6/9] target-ppc: add lxvh8x instruction, (continued)
- [Qemu-ppc] [PATCH v4 5/9] target-ppc: improve stxvw4x implementation, Nikunj A Dadhania, 2016/09/28
- [Qemu-ppc] [PATCH v4 8/9] target-ppc: add lxvb16x instruction, Nikunj A Dadhania, 2016/09/28
- [Qemu-ppc] [PATCH v4 7/9] target-ppc: add stxvh8x instruction, Nikunj A Dadhania, 2016/09/28
- [Qemu-ppc] [PATCH v4 9/9] target-ppc: add stxvb16x instruction, Nikunj A Dadhania, 2016/09/28
- Re: [Qemu-ppc] [PATCH v4 0/9] POWER9 TCG enablements - part4, Nikunj A Dadhania, 2016/09/28
- Re: [Qemu-ppc] [PATCH v4 0/9] POWER9 TCG enablements - part4,
Thomas Huth <=