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Re: [Qemu-ppc] [PATCH v2 0/3] POWER9 TCG enablements - part10


From: David Gibson
Subject: Re: [Qemu-ppc] [PATCH v2 0/3] POWER9 TCG enablements - part10
Date: Tue, 10 Jan 2017 11:26:37 +1100
User-agent: Mutt/1.7.1 (2016-10-04)

On Mon, Jan 09, 2017 at 07:56:12PM +0530, Nikunj A Dadhania wrote:
> This series contains 11 new instructions for POWER9 ISA3.0
>      VSX Scalar Convert
>      VSX Scalar Add QP
> 
> Changelog:
> v1: 
> * xsaddqp, xscv[dpqp, qpdp] instructions use register numbering 0-31, this 
> needs
>   to be handled in the decoding. ISA 3.0 documents to use them as VSR[VRA + 
> 32], 
>   and likewise for other registers. 
> 
> v0:
>    Rebase and update reviewed-by

Applied to ppc-for-2.9, replacing the earlier versions.

> 
> 
> Bharata B Rao (3):
>   target-ppc: Add xsaddqp instructions
>   target-ppc: Add xscvdpqp instruction
>   target-ppc: Add xscvqpdp instruction
> 
>  target/ppc/fpu_helper.c             | 109 
> ++++++++++++++++++++++++++++++++++++
>  target/ppc/helper.h                 |   3 +
>  target/ppc/internal.h               |   1 +
>  target/ppc/translate/vsx-impl.inc.c |   3 +
>  target/ppc/translate/vsx-ops.inc.c  |   3 +
>  5 files changed, 119 insertions(+)
> 

-- 
David Gibson                    | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au  | minimalist, thank you.  NOT _the_ _other_
                                | _way_ _around_!
http://www.ozlabs.org/~dgibson

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