[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Qemu-ppc] [PATCH v5 6/7] ppc: Implement bcdtrunc. instruction
From: |
David Gibson |
Subject: |
Re: [Qemu-ppc] [PATCH v5 6/7] ppc: Implement bcdtrunc. instruction |
Date: |
Thu, 12 Jan 2017 14:10:34 +1100 |
User-agent: |
Mutt/1.7.1 (2016-10-04) |
On Tue, Jan 10, 2017 at 12:10:13AM -0200, Jose Ricardo Ziviani wrote:
> bcdtrunc.: Decimal integer truncate. Given a BCD number in vrb and the
> number of bytes to truncate in vra, the return register will have vrb
> with such bits truncated.
>
> Signed-off-by: Jose Ricardo Ziviani <address@hidden>
> ---
> target/ppc/helper.h | 1 +
> target/ppc/int_helper.c | 37
> +++++++++++++++++++++++++++++++++++++
> target/ppc/translate/vmx-impl.inc.c | 5 +++++
> target/ppc/translate/vmx-ops.inc.c | 4 ++--
> 4 files changed, 45 insertions(+), 2 deletions(-)
>
> diff --git a/target/ppc/helper.h b/target/ppc/helper.h
> index d1db462..db17917 100644
> --- a/target/ppc/helper.h
> +++ b/target/ppc/helper.h
> @@ -401,6 +401,7 @@ DEF_HELPER_3(bcdsetsgn, i32, avr, avr, i32)
> DEF_HELPER_4(bcds, i32, avr, avr, avr, i32)
> DEF_HELPER_4(bcdus, i32, avr, avr, avr, i32)
> DEF_HELPER_4(bcdsr, i32, avr, avr, avr, i32)
> +DEF_HELPER_4(bcdtrunc, i32, avr, avr, avr, i32)
>
> DEF_HELPER_2(xsadddp, void, env, i32)
> DEF_HELPER_2(xsaddqp, void, env, i32)
> diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
> index b184063..06b14d5 100644
> --- a/target/ppc/int_helper.c
> +++ b/target/ppc/int_helper.c
> @@ -3223,6 +3223,43 @@ uint32_t helper_bcdsr(ppc_avr_t *r, ppc_avr_t *a,
> ppc_avr_t *b, uint32_t ps)
> return cr;
> }
>
> +uint32_t helper_bcdtrunc(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t
> ps)
> +{
> + uint64_t mask;
> + uint32_t ox_flag = 0;
> +#if defined(HOST_WORDS_BIGENDIAN)
> + int i = a->s16[3] + 1;
> +#else
> + int i = a->s16[4] + 1;
> +#endif
> + ppc_avr_t ret = *b;
> +
> + if (bcd_is_valid(b) == false) {
> + return CRF_SO;
> + }
> +
> + if (i > 16 && i < 32) {
> + if (ret.u64[HI_IDX] >> (i * 4 - 64)) {
> + ox_flag = CRF_SO;
> + }
You can simplify this by just checking ret.u64[HI_IDX] & ~mask before
you apply the mast.
> +
> + mask = (uint64_t)-1 >> (128 - i * 4);
> + ret.u64[HI_IDX] &= mask;
> + } else if (i >= 0 && i <= 16) {
> + if (ret.u64[HI_IDX] || (i < 16 && ret.u64[LO_IDX] >> (i * 4))) {
> + ox_flag = CRF_SO;
> + }
> +
> + mask = (uint64_t)-1 >> (64 - i * 4);
Similarly here.
> + ret.u64[LO_IDX] &= mask;
> + ret.u64[HI_IDX] = 0;
> + }
> + bcd_put_digit(&ret, bcd_preferred_sgn(bcd_get_sgn(b), ps), 0);
> + *r = ret;
> +
> + return bcd_cmp_zero(&ret) | ox_flag;
> +}
> +
> void helper_vsbox(ppc_avr_t *r, ppc_avr_t *a)
> {
> int i;
> diff --git a/target/ppc/translate/vmx-impl.inc.c
> b/target/ppc/translate/vmx-impl.inc.c
> index 451abb5..1683f42 100644
> --- a/target/ppc/translate/vmx-impl.inc.c
> +++ b/target/ppc/translate/vmx-impl.inc.c
> @@ -1019,6 +1019,7 @@ GEN_BCD(bcdcpsgn);
> GEN_BCD(bcds);
> GEN_BCD(bcdus);
> GEN_BCD(bcdsr);
> +GEN_BCD(bcdtrunc);
>
> static void gen_xpnd04_1(DisasContext *ctx)
> {
> @@ -1097,6 +1098,10 @@ GEN_VXFORM_DUAL(vsubudm, PPC2_ALTIVEC_207, PPC_NONE, \
> bcds, PPC_NONE, PPC2_ISA300)
> GEN_VXFORM_DUAL(vsubuwm, PPC_ALTIVEC, PPC_NONE, \
> bcdus, PPC_NONE, PPC2_ISA300)
> +GEN_VXFORM_DUAL(vsubsbs, PPC_ALTIVEC, PPC_NONE, \
> + bcdtrunc, PPC_NONE, PPC2_ISA300)
> +GEN_VXFORM_DUAL(vsubuqm, PPC2_ALTIVEC_207, PPC_NONE, \
> + bcdtrunc, PPC_NONE, PPC2_ISA300)
>
> static void gen_vsbox(DisasContext *ctx)
> {
> diff --git a/target/ppc/translate/vmx-ops.inc.c
> b/target/ppc/translate/vmx-ops.inc.c
> index fa9c996..e6167a4 100644
> --- a/target/ppc/translate/vmx-ops.inc.c
> +++ b/target/ppc/translate/vmx-ops.inc.c
> @@ -143,14 +143,14 @@ GEN_VXFORM(vaddsws, 0, 14),
> GEN_VXFORM_DUAL(vsububs, bcdadd, 0, 24, PPC_ALTIVEC, PPC_NONE),
> GEN_VXFORM_DUAL(vsubuhs, bcdsub, 0, 25, PPC_ALTIVEC, PPC_NONE),
> GEN_VXFORM(vsubuws, 0, 26),
> -GEN_VXFORM(vsubsbs, 0, 28),
> +GEN_VXFORM_DUAL(vsubsbs, bcdtrunc, 0, 28, PPC_NONE, PPC2_ISA300),
> GEN_VXFORM(vsubshs, 0, 29),
> GEN_VXFORM_DUAL(vsubsws, xpnd04_2, 0, 30, PPC_ALTIVEC, PPC_NONE),
> GEN_VXFORM_207(vadduqm, 0, 4),
> GEN_VXFORM_207(vaddcuq, 0, 5),
> GEN_VXFORM_DUAL(vaddeuqm, vaddecuq, 30, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
> -GEN_VXFORM_207(vsubuqm, 0, 20),
> GEN_VXFORM_207(vsubcuq, 0, 21),
> +GEN_VXFORM_DUAL(vsubuqm, bcdtrunc, 0, 20, PPC2_ALTIVEC_207, PPC2_ISA300),
> GEN_VXFORM_DUAL(vsubeuqm, vsubecuq, 31, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
> GEN_VXFORM(vrlb, 2, 0),
> GEN_VXFORM(vrlh, 2, 1),
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
signature.asc
Description: PGP signature
- [Qemu-ppc] [PATCH v5 0/7] POWER9 TCG enablements - BCD functions - final part, Jose Ricardo Ziviani, 2017/01/09
- [Qemu-ppc] [PATCH v5 1/7] host-utils: Move 128-bit guard macro to .c file, Jose Ricardo Ziviani, 2017/01/09
- [Qemu-ppc] [PATCH v5 2/7] host-utils: Implement unsigned quadword left/right shift and unit tests, Jose Ricardo Ziviani, 2017/01/09
- [Qemu-ppc] [PATCH v5 3/7] ppc: Implement bcds. instruction, Jose Ricardo Ziviani, 2017/01/09
- [Qemu-ppc] [PATCH v5 4/7] ppc: Implement bcdus. instruction, Jose Ricardo Ziviani, 2017/01/09
- [Qemu-ppc] [PATCH v5 5/7] ppc: Implement bcdsr. instruction, Jose Ricardo Ziviani, 2017/01/09
- [Qemu-ppc] [PATCH v5 6/7] ppc: Implement bcdtrunc. instruction, Jose Ricardo Ziviani, 2017/01/09
- Re: [Qemu-ppc] [PATCH v5 6/7] ppc: Implement bcdtrunc. instruction,
David Gibson <=
- [Qemu-ppc] [PATCH v5 7/7] ppc: Implement bcdutrunc. instruction, Jose Ricardo Ziviani, 2017/01/09
- Re: [Qemu-ppc] [PATCH v5 0/7] POWER9 TCG enablements - BCD functions - final part, David Gibson, 2017/01/11