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[Qemu-ppc] [PULL 17/50] target/ppc: update ca32 in arithmetic add
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 17/50] target/ppc: update ca32 in arithmetic add |
Date: |
Wed, 1 Mar 2017 15:43:32 +1100 |
From: Nikunj A Dadhania <address@hidden>
Adds routine to compute ca32 - gen_op_arith_compute_ca32
For 64-bit mode use the compute ca32 routine. While for 32-bit mode, CA
and CA32 will have same value.
Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target/ppc/translate.c | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index be7378b..eba83ef 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -816,6 +816,23 @@ static inline void gen_op_arith_compute_ov(DisasContext
*ctx, TCGv arg0,
tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
}
+static inline void gen_op_arith_compute_ca32(DisasContext *ctx,
+ TCGv res, TCGv arg0, TCGv arg1,
+ int sub)
+{
+ TCGv t0;
+
+ if (!is_isa300(ctx)) {
+ return;
+ }
+
+ t0 = tcg_temp_new();
+ tcg_gen_xor_tl(t0, arg0, arg1);
+ tcg_gen_xor_tl(t0, t0, res);
+ tcg_gen_extract_tl(cpu_ca32, t0, 32, 1);
+ tcg_temp_free(t0);
+}
+
/* Common add function */
static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
TCGv arg2, bool add_ca, bool compute_ca,
@@ -842,6 +859,9 @@ static inline void gen_op_arith_add(DisasContext *ctx, TCGv
ret, TCGv arg1,
tcg_temp_free(t1);
tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
+ if (is_isa300(ctx)) {
+ tcg_gen_mov_tl(cpu_ca32, cpu_ca);
+ }
} else {
TCGv zero = tcg_const_tl(0);
if (add_ca) {
@@ -850,6 +870,7 @@ static inline void gen_op_arith_add(DisasContext *ctx, TCGv
ret, TCGv arg1,
} else {
tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
}
+ gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, 0);
tcg_temp_free(zero);
}
} else {
--
2.9.3
- [Qemu-ppc] [PULL 06/50] sysemu: support up to 1024 vCPUs, (continued)
- [Qemu-ppc] [PULL 06/50] sysemu: support up to 1024 vCPUs, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 10/50] target/ppc: SDR1 is a hypervisor resource, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 18/50] target/ppc: update ca32 in arithmetic substract, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 09/50] target/ppc: Merge cpu_ppc_set_vhyp() with cpu_ppc_set_papr(), David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 19/50] target/ppc: update overflow flags for add/sub, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 14/50] target/ppc: Remove the function ppc_hash64_set_sdr1(), David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 03/50] PCI: add missing classes in pci_ids.h to build device tree, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 20/50] target/ppc: use tcg ops for neg instruction, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 04/50] spapr: generate DT node names, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 16/50] target/ppc: support for 32-bit carry and overflow, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 17/50] target/ppc: update ca32 in arithmetic add,
David Gibson <=
- [Qemu-ppc] [PULL 15/50] target/ppc: Correct SDR1 masking, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 07/50] target/ppc: Fix KVM-HV HPTE accessors, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 34/50] ppc/xics: remove xics_find_source(), David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 24/50] spapr/pci: populate PCI DT in reverse order, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 33/50] ppc/xics: use the QOM interface to resend irqs, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 22/50] target/ppc: add ov32 flag in divide operations, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 42/50] ppc/xics: simplify spapr_dt_xics() interface, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 47/50] ppc/xics: move ics-simple post_load under the machine, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 27/50] ppc/xics: remove set_nr_servers() handler from XICSStateClass, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 49/50] ppc/xics: rename 'ICPState *' variables to 'icp', David Gibson, 2017/02/28