Re: [Qemu-ppc] [PATCH for-2.10 2/2] target/ppc: Add stub implementation of the PSSCR

[David Gibson]

On Tue, Aug 08, 2017 at 12:54:51PM +0200, Greg Kurz wrote:
> On Tue, 8 Aug 2017 11:19:58 +0200
> Cédric Le Goater <address@hidden> wrote:
> 
> > On 08/08/2017 08:08 AM, David Gibson wrote:
> > > The PSSCR register added in POWER9 controls certain power saving mode
> > > behaviours.  Mostly, it's not relevant to TCG, however because qemu
> > > doesn't know about it yet, it doesn't synchronize the state with KVM,
> > > and thus it doesn't get migrated.
> > > 
> > > To fix that, this adds a minimal stub implementation of the register.
> > > This isn't complete, even to the extent that an implementation is
> > > possible in TCG, just enough to get migration working.  We need to
> > > come back later and at least properly filter the various fields in the
> > > register based on privilege level.  
> > 
> > yes a lot of the fields are only accessible to the hypervisor, and the 
> > hypervisor also uses a different SPR number to access the PSSCR bits.
> > 
> 
> This patch uses 0x357 (855) which is the SPR number for hypervisor state
> access. But, yes, part of the register is also accessible in privileged
> non-hypervisor state with SPR number 0x337 (823). This will have to be
> covered later, but for now:

Yeah, I know.

-- 
David Gibson                    | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au  | minimalist, thank you.  NOT _the_ _other_
                                | _way_ _around_!
http://www.ozlabs.org/~dgibson

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