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Re: [Qemu-ppc] [Qemu-devel] [PATCH 0/2] Add 8-byte wide AMD flash suppor
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From: |
Peter Maydell |
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Subject: |
Re: [Qemu-ppc] [Qemu-devel] [PATCH 0/2] Add 8-byte wide AMD flash support, partial interleaving |
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Date: |
Tue, 31 Oct 2017 17:00:45 +0000 |
On 31 October 2017 at 15:44, Mike Nawrocki
<address@hidden> wrote:
> This patch set does a few things. First, it switches the AMD CFI flash MMIO
> operations from the old MMIO API to the new one. Second, it enables 8-byte
> wide flash arrays. Finally, it supports rudimentary interleaving of notional
> flash "chips". It is expected that commands will be sent to all "chips"
> simultaneously. See the example in the second patch for more details. This
> behavior is used by drivers for the PPMC7400 PowerPC evaluation board.
I'm confused by the interleaving part. Can you explain how this
differs from the interleaving we already support in pflash_cfi01.c
via setting width, device-width and max-device-width ? (see the comment
in the pflash_cfi01_properties[] array about how those settings
interact). If it is the same thing, we should really implement it
in the same way for both kinds of flash device.
thanks
-- PMM