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[Qemu-ppc] [PATCH for-2.13 06/13] target/ppc: Move page size setup to he
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PATCH for-2.13 06/13] target/ppc: Move page size setup to helper function |
Date: |
Thu, 5 Apr 2018 12:14:30 +1000 |
Initialization of the env->sps structure at the end of instance_init is
specific to the 64-bit hash MMU, so move the code into a helper function
in mmu-hash64.c.
We also create a corresponding function to be called at finalize time -
it's empty for now, but we'll need it shortly.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
---
target/ppc/mmu-hash64.c | 29 +++++++++++++++++++++++++++++
target/ppc/mmu-hash64.h | 11 +++++++++++
target/ppc/translate_init.c | 29 +++++++++--------------------
3 files changed, 49 insertions(+), 20 deletions(-)
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index a87fa7c83f..4cb7d1cf07 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -1095,3 +1095,32 @@ void helper_store_lpcr(CPUPPCState *env, target_ulong
val)
ppc_hash64_update_rmls(cpu);
ppc_hash64_update_vrma(cpu);
}
+
+void ppc_hash64_init(PowerPCCPU *cpu)
+{
+ CPUPPCState *env = &cpu->env;
+ PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
+
+ if (pcc->sps) {
+ env->sps = *pcc->sps;
+ } else if (env->mmu_model & POWERPC_MMU_64) {
+ /* Use default sets of page sizes. We don't support MPSS */
+ static const struct ppc_segment_page_sizes defsps = {
+ .sps = {
+ { .page_shift = 12, /* 4K */
+ .slb_enc = 0,
+ .enc = { { .page_shift = 12, .pte_enc = 0 } }
+ },
+ { .page_shift = 24, /* 16M */
+ .slb_enc = 0x100,
+ .enc = { { .page_shift = 24, .pte_enc = 0 } }
+ },
+ },
+ };
+ env->sps = defsps;
+ }
+}
+
+void ppc_hash64_finalize(PowerPCCPU *cpu)
+{
+}
diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h
index 95a8c330d6..074ded4c27 100644
--- a/target/ppc/mmu-hash64.h
+++ b/target/ppc/mmu-hash64.h
@@ -19,6 +19,8 @@ unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu,
uint64_t pte0, uint64_t pte1);
void ppc_hash64_update_vrma(PowerPCCPU *cpu);
void ppc_hash64_update_rmls(PowerPCCPU *cpu);
+void ppc_hash64_init(PowerPCCPU *cpu);
+void ppc_hash64_finalize(PowerPCCPU *cpu);
#endif
/*
@@ -136,4 +138,13 @@ static inline uint64_t ppc_hash64_hpte1(PowerPCCPU *cpu,
#endif /* CONFIG_USER_ONLY */
+#if defined(CONFIG_USER_ONLY) || !defined(TARGET_PPC64)
+static inline void ppc_hash64_init(PowerPCCPU *cpu)
+{
+}
+static inline void ppc_hash64_finalize(PowerPCCPU *cpu)
+{
+}
+#endif
+
#endif /* MMU_HASH64_H */
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index 99be6fcd68..aa63a5dcb3 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -10464,26 +10464,14 @@ static void ppc_cpu_instance_init(Object *obj)
env->has_hv_mode = !!(env->msr_mask & MSR_HVB);
#endif
-#if defined(TARGET_PPC64)
- if (pcc->sps) {
- env->sps = *pcc->sps;
- } else if (env->mmu_model & POWERPC_MMU_64) {
- /* Use default sets of page sizes. We don't support MPSS */
- static const struct ppc_segment_page_sizes defsps = {
- .sps = {
- { .page_shift = 12, /* 4K */
- .slb_enc = 0,
- .enc = { { .page_shift = 12, .pte_enc = 0 } }
- },
- { .page_shift = 24, /* 16M */
- .slb_enc = 0x100,
- .enc = { { .page_shift = 24, .pte_enc = 0 } }
- },
- },
- };
- env->sps = defsps;
- }
-#endif /* defined(TARGET_PPC64) */
+ ppc_hash64_init(cpu);
+}
+
+static void ppc_cpu_instance_finalize(Object *obj)
+{
+ PowerPCCPU *cpu = POWERPC_CPU(obj);
+
+ ppc_hash64_finalize(cpu);
}
static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr)
@@ -10601,6 +10589,7 @@ static const TypeInfo ppc_cpu_type_info = {
.parent = TYPE_CPU,
.instance_size = sizeof(PowerPCCPU),
.instance_init = ppc_cpu_instance_init,
+ .instance_finalize = ppc_cpu_instance_finalize,
.abstract = true,
.class_size = sizeof(PowerPCCPUClass),
.class_init = ppc_cpu_class_init,
--
2.14.3
- [Qemu-ppc] [PATCH for-2.13 00/13] target/ppc: Assorted cpu cleanups (esp. hash64 MMU), David Gibson, 2018/04/04
- [Qemu-ppc] [PATCH for-2.13 02/13] target/ppc: Simplify cpu valid check in ppc_cpu_realize, David Gibson, 2018/04/04
- [Qemu-ppc] [PATCH for-2.13 06/13] target/ppc: Move page size setup to helper function,
David Gibson <=
- [Qemu-ppc] [PATCH for-2.13 11/13] target/ppc: Remove unnecessary POWERPC_MMU_V3 flag from mmu_model, David Gibson, 2018/04/04
- [Qemu-ppc] [PATCH for-2.13 01/13] target/ppc: Standardize instance_init and realize function names, David Gibson, 2018/04/04
- [Qemu-ppc] [PATCH for-2.13 05/13] target/ppc: Remove fallback 64k pagesize information, David Gibson, 2018/04/04
- [Qemu-ppc] [PATCH for-2.13 03/13] target/ppc: Pass cpu instead of env to ppc_create_page_sizes_prop(), David Gibson, 2018/04/04
- [Qemu-ppc] [PATCH for-2.13 08/13] target/ppc: Make hash64_opts field mandatory for 64-bit hash MMUs, David Gibson, 2018/04/04
- [Qemu-ppc] [PATCH for-2.13 10/13] target/ppc: Fold ci_large_pages flag into PPCHash64Options, David Gibson, 2018/04/04
- [Qemu-ppc] [PATCH for-2.13 04/13] target/ppc: Avoid taking "env" parameter to mmu-hash64 functions, David Gibson, 2018/04/04
- [Qemu-ppc] [PATCH for-2.13 09/13] target/ppc: Move 1T segment and AMR options to PPCHash64Options, David Gibson, 2018/04/04