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Re: [Qemu-ppc] [RFC PATCH] target/ppc: extend eieio for POWER9
From: |
David Gibson |
Subject: |
Re: [Qemu-ppc] [RFC PATCH] target/ppc: extend eieio for POWER9 |
Date: |
Tue, 5 Jun 2018 09:10:33 +1000 |
User-agent: |
Mutt/1.9.5 (2018-04-13) |
On Mon, Jun 04, 2018 at 07:20:39PM +0200, Cédric Le Goater wrote:
> POWER9 introduced a new variant of the eieio instruction using bit 6
> as a hint to tell the CPU it is a store-forwarding barrier.
>
> The usage of this eieio extension was recently added in Linux 4.17
> which activated the "support for a store forwarding barrier at kernel
> entry/exit".
>
> This loosen the QEMU eieio instruction mask to boot newer kernel but I
> think we should be adding a new *eieio* instruction specific to POWER9
> instead. I just don't know how to define an instruction variant with
> the same op code for an ISA version. Any idea ?
I think you're right that this should be done slightly differently.
I think you can do that by adding a new instruction mask bit; say
PPC2_MEM_EIEIO2 or whatever. You leave the existing GEN_HANDLER as
is, add another GEN_HANDLER_E with the new mask dependent on the new
bit, then make sure POWER9 has the new bit set, but not the old one.
>
> Signed-off-by: Cédric Le Goater <address@hidden>
> ---
>
> target/ppc/translate.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> Index: qemu-powernv-2.13.git/target/ppc/translate.c
> ===================================================================
> --- qemu-powernv-2.13.git.orig/target/ppc/translate.c
> +++ qemu-powernv-2.13.git/target/ppc/translate.c
> @@ -6496,7 +6496,7 @@ GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00
> GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
> GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
> GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
> -GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
> +GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO),
> GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
> GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
> GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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