[Qemu-ppc] [PATCH v4 20/28] spapr: introduce a 'pseries-3.0-xive' QEMU machine

[Cédric Le Goater]

The interrupt mode is statically defined to XIVE only for this machine.
The guest OS is required to have support for the XIVE exploitation
mode of the POWER9 interrupt controller.

Signed-off-by: Cédric Le Goater <address@hidden>
---
 include/hw/ppc/spapr_irq.h |  1 +
 hw/ppc/spapr.c             | 35 ++++++++++++++++++++++++++++++-----
 hw/ppc/spapr_irq.c         |  3 +++
 3 files changed, 34 insertions(+), 5 deletions(-)

diff --git a/include/hw/ppc/spapr_irq.h b/include/hw/ppc/spapr_irq.h
index 8046cbd83d61..85829928a9c4 100644
--- a/include/hw/ppc/spapr_irq.h
+++ b/include/hw/ppc/spapr_irq.h
@@ -31,6 +31,7 @@ typedef struct sPAPRPIrqRange {
 typedef struct sPAPRIrq {
     uint32_t    nr_irqs;
     const sPAPRPIrqRange *ranges;
+    uint8_t     ov5;
 
     void (*init)(sPAPRMachineState *spapr, uint32_t nr_servers, Error **errp);
     int (*assign)(sPAPRMachineState *spapr, uint32_t range, uint32_t irq,
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 3340264e4cfb..2774b53f169e 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -1060,12 +1060,14 @@ static void spapr_dt_rtas(sPAPRMachineState *spapr, 
void *fdt)
     spapr_dt_rtas_tokens(fdt, rtas);
 }
 
-/* Prepare ibm,arch-vec-5-platform-support, which indicates the MMU features
- * that the guest may request and thus the valid values for bytes 24..26 of
- * option vector 5: */
-static void spapr_dt_ov5_platform_support(void *fdt, int chosen)
+/* Prepare ibm,arch-vec-5-platform-support, which indicates the MMU
+ * and the XIVE features that the guest may request and thus the valid
+ * values for bytes 23..26 of option vector 5: */
+static void spapr_dt_ov5_platform_support(sPAPRMachineState *spapr, void *fdt,
+                                          int chosen)
 {
     PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu);
+    sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
 
     char val[2 * 4] = {
         23, 0x00, /* Xive mode, filled in below. */
@@ -1086,7 +1088,10 @@ static void spapr_dt_ov5_platform_support(void *fdt, int 
chosen)
         } else {
             val[3] = 0x00; /* Hash */
         }
+        val[1] = smc->irq->ov5;
     } else {
+        val[1] = smc->irq->ov5;
+
         /* V3 MMU supports both hash and radix in tcg (with dynamic switching) 
*/
         val[3] = 0xC0;
     }
@@ -1154,7 +1159,7 @@ static void spapr_dt_chosen(sPAPRMachineState *spapr, 
void *fdt)
         _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path));
     }
 
-    spapr_dt_ov5_platform_support(fdt, chosen);
+    spapr_dt_ov5_platform_support(spapr, fdt, chosen);
 
     g_free(stdout_path);
     g_free(bootlist);
@@ -2577,6 +2582,11 @@ static void spapr_machine_init(MachineState *machine)
     /* advertise support for ibm,dyamic-memory-v2 */
     spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2);
 
+    /* advertise XIVE */
+    if (smc->irq->ov5) {
+        spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT);
+    }
+
     /* init CPUs */
     spapr_init_cpus(spapr);
 
@@ -3916,6 +3926,21 @@ static void spapr_machine_3_0_class_options(MachineClass 
*mc)
 
 DEFINE_SPAPR_MACHINE(3_0, "3.0", true);
 
+static void spapr_machine_3_0_xive_instance_options(MachineState *machine)
+{
+    spapr_machine_3_0_instance_options(machine);
+}
+
+static void spapr_machine_3_0_xive_class_options(MachineClass *mc)
+{
+    sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
+
+    spapr_machine_3_0_class_options(mc);
+    smc->irq = &spapr_irq_xive;
+}
+
+DEFINE_SPAPR_MACHINE(3_0_xive, "3.0-xive", false);
+
 /*
  * pseries-2.12
  */
diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c
index 266f7db3be7b..745c78024d6f 100644
--- a/hw/ppc/spapr_irq.c
+++ b/hw/ppc/spapr_irq.c
@@ -256,6 +256,7 @@ static Object 
*spapr_irq_cpu_intc_create_legacy(sPAPRMachineState *spapr,
 
 sPAPRIrq spapr_irq_legacy = {
     .nr_irqs     = XICS_IRQS_SPAPR,
+    .ov5         = 0x0, /* XICS only */
     .init        = spapr_irq_init_legacy,
     .assign      = spapr_irq_assign_legacy,
     .alloc       = spapr_irq_alloc_legacy,
@@ -522,6 +523,7 @@ static const sPAPRPIrqRange spapr_irq_ranges_xics[] = {
 
 sPAPRIrq spapr_irq_xics = {
     .nr_irqs     = 0x1000,
+    .ov5         = 0x0, /* XICS only */
     .init        = spapr_irq_init_xics,
     .ranges      = spapr_irq_ranges_xics,
     .assign      = spapr_irq_assign_xics,
@@ -743,6 +745,7 @@ static const sPAPRPIrqRange spapr_irq_ranges_xive[] = {
 
 sPAPRIrq spapr_irq_xive = {
     .nr_irqs     = 0x2000,
+    .ov5         = 0x40, /* XIVE exploitation mode only */
     .init        = spapr_irq_init_xive,
     .ranges      = spapr_irq_ranges_xive,
     .assign      = spapr_irq_assign_xive,
-- 
2.13.6