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Re: [Qemu-ppc] [Qemu-devel] [PATCH v2 5/8] hw/timer: Add basic M41T80 em
From: |
David Gibson |
Subject: |
Re: [Qemu-ppc] [Qemu-devel] [PATCH v2 5/8] hw/timer: Add basic M41T80 emulation |
Date: |
Fri, 15 Jun 2018 14:08:30 +1000 |
User-agent: |
Mutt/1.10.0 (2018-05-17) |
On Thu, Jun 14, 2018 at 09:54:41AM +0200, BALATON Zoltan wrote:
> On Thu, 14 Jun 2018, David Gibson wrote:
> > On Wed, Jun 13, 2018 at 04:13:57PM +0200, BALATON Zoltan wrote:
> > > I don't see the problem. The addr register selects the register to read or
> > > write. It is set by the first write when the device is accessed the first
> > > time (this is denoted by addr == -1 (or really any negative value). The
> > > device has 20 registers and trying to read any register outside addr
> > > between
> > > 0-19 will result in returning 0 and logging a warning about invalid
> > > register
> > > in m41t80_recv. What could fail here when guest sends garbage? It will set
> > > addr to invalid value and try to read non-exitent register and get an
> > > error
> > > just like for any other nonexistent value of addr (or start to read from
> > > register 0 if it manages to set a negative value). All writes of registers
> > > are ignored currently (except setting addr by the first write). What
> > > should
> > > be enforced here?
> >
> > Ah, I see your point. I mean strictly we should match the hardware
> > behaviour if you write garbage addresses here, but really I don't
> > think it matters much.
>
> Problem is like usual I have no idea what the real hardware does. I've only
> seen the datasheet, never seen real device and have no way to test. All the
> clients I've tested seem to be OK with the current emulation so unless
> someone has more info on how this should work I think we can live with this
> version and then fix it later if found to be needed.
Ok, fair enough.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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- Re: [Qemu-ppc] [Qemu-devel] [PATCH v2 1/8] ppc4xx_i2c: Clean up and improve error logging, (continued)
- [Qemu-ppc] [PATCH v2 5/8] hw/timer: Add basic M41T80 emulation, BALATON Zoltan, 2018/06/06
- Re: [Qemu-ppc] [Qemu-devel] [PATCH v2 5/8] hw/timer: Add basic M41T80 emulation, Philippe Mathieu-Daudé, 2018/06/06
- Re: [Qemu-ppc] [Qemu-devel] [PATCH v2 5/8] hw/timer: Add basic M41T80 emulation, BALATON Zoltan, 2018/06/06
- Re: [Qemu-ppc] [Qemu-devel] [PATCH v2 5/8] hw/timer: Add basic M41T80 emulation, David Gibson, 2018/06/13
- Re: [Qemu-ppc] [Qemu-devel] [PATCH v2 5/8] hw/timer: Add basic M41T80 emulation, BALATON Zoltan, 2018/06/13
- Re: [Qemu-ppc] [Qemu-devel] [PATCH v2 5/8] hw/timer: Add basic M41T80 emulation, David Gibson, 2018/06/13
- Re: [Qemu-ppc] [Qemu-devel] [PATCH v2 5/8] hw/timer: Add basic M41T80 emulation, BALATON Zoltan, 2018/06/13
- Re: [Qemu-ppc] [Qemu-devel] [PATCH v2 5/8] hw/timer: Add basic M41T80 emulation, David Gibson, 2018/06/13
- Re: [Qemu-ppc] [Qemu-devel] [PATCH v2 5/8] hw/timer: Add basic M41T80 emulation, BALATON Zoltan, 2018/06/14
- Re: [Qemu-ppc] [Qemu-devel] [PATCH v2 5/8] hw/timer: Add basic M41T80 emulation,
David Gibson <=
Re: [Qemu-ppc] [PATCH v2 5/8] hw/timer: Add basic M41T80 emulation, Cédric Le Goater, 2018/06/08
[Qemu-ppc] [PATCH v2 4/8] ppc4xx_i2c: Rewrite to model hardware more closely, BALATON Zoltan, 2018/06/06
[Qemu-ppc] [PATCH v2 2/8] ppc4xx_i2c: Move register state to private struct and remove unimplemented sdata and intr registers, BALATON Zoltan, 2018/06/06