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[Qemu-ppc] [PULL 17/38] target/ppc: Optimise VSX_LOAD_SCALAR_DS and VSX_
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From: |
David Gibson |
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Subject: |
[Qemu-ppc] [PULL 17/38] target/ppc: Optimise VSX_LOAD_SCALAR_DS and VSX_VECTOR_LOAD_STORE |
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Date: |
Wed, 22 May 2019 14:45:39 +1000 |
From: Anton Blanchard <address@hidden>
A few small optimisations:
In VSX_LOAD_SCALAR_DS() we can don't need to read the VSR via
get_cpu_vsrh().
Split VSX_VECTOR_LOAD_STORE() into two functions. Loads only need to
write the VSRs (set_cpu_vsr*()) and stores only need to read the VSRs
(get_cpu_vsr*())
Thanks to Mark Cave-Ayland for the suggestions.
Signed-off-by: Anton Blanchard <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target/ppc/translate/vsx-impl.inc.c | 68 ++++++++++++++++++++++++-----
1 file changed, 58 insertions(+), 10 deletions(-)
diff --git a/target/ppc/translate/vsx-impl.inc.c
b/target/ppc/translate/vsx-impl.inc.c
index 4b8f6cefe3..c39829cf33 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -227,7 +227,7 @@ static void gen_lxvb16x(DisasContext *ctx)
tcg_temp_free_i64(xtl);
}
-#define VSX_VECTOR_LOAD_STORE(name, op, indexed) \
+#define VSX_VECTOR_LOAD(name, op, indexed) \
static void gen_##name(DisasContext *ctx) \
{ \
int xt; \
@@ -254,8 +254,6 @@ static void gen_##name(DisasContext *ctx)
\
} \
xth = tcg_temp_new_i64(); \
xtl = tcg_temp_new_i64(); \
- get_cpu_vsrh(xth, xt); \
- get_cpu_vsrl(xtl, xt); \
gen_set_access_type(ctx, ACCESS_INT); \
EA = tcg_temp_new(); \
if (indexed) { \
@@ -281,10 +279,61 @@ static void gen_##name(DisasContext *ctx)
\
tcg_temp_free_i64(xtl); \
}
-VSX_VECTOR_LOAD_STORE(lxv, ld_i64, 0)
-VSX_VECTOR_LOAD_STORE(stxv, st_i64, 0)
-VSX_VECTOR_LOAD_STORE(lxvx, ld_i64, 1)
-VSX_VECTOR_LOAD_STORE(stxvx, st_i64, 1)
+VSX_VECTOR_LOAD(lxv, ld_i64, 0)
+VSX_VECTOR_LOAD(lxvx, ld_i64, 1)
+
+#define VSX_VECTOR_STORE(name, op, indexed) \
+static void gen_##name(DisasContext *ctx) \
+{ \
+ int xt; \
+ TCGv EA; \
+ TCGv_i64 xth; \
+ TCGv_i64 xtl; \
+ \
+ if (indexed) { \
+ xt = xT(ctx->opcode); \
+ } else { \
+ xt = DQxT(ctx->opcode); \
+ } \
+ \
+ if (xt < 32) { \
+ if (unlikely(!ctx->vsx_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VSXU); \
+ return; \
+ } \
+ } else { \
+ if (unlikely(!ctx->altivec_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VPU); \
+ return; \
+ } \
+ } \
+ xth = tcg_temp_new_i64(); \
+ xtl = tcg_temp_new_i64(); \
+ get_cpu_vsrh(xth, xt); \
+ get_cpu_vsrl(xtl, xt); \
+ gen_set_access_type(ctx, ACCESS_INT); \
+ EA = tcg_temp_new(); \
+ if (indexed) { \
+ gen_addr_reg_index(ctx, EA); \
+ } else { \
+ gen_addr_imm_index(ctx, EA, 0x0F); \
+ } \
+ if (ctx->le_mode) { \
+ tcg_gen_qemu_##op(xtl, EA, ctx->mem_idx, MO_LEQ); \
+ tcg_gen_addi_tl(EA, EA, 8); \
+ tcg_gen_qemu_##op(xth, EA, ctx->mem_idx, MO_LEQ); \
+ } else { \
+ tcg_gen_qemu_##op(xth, EA, ctx->mem_idx, MO_BEQ); \
+ tcg_gen_addi_tl(EA, EA, 8); \
+ tcg_gen_qemu_##op(xtl, EA, ctx->mem_idx, MO_BEQ); \
+ } \
+ tcg_temp_free(EA); \
+ tcg_temp_free_i64(xth); \
+ tcg_temp_free_i64(xtl); \
+}
+
+VSX_VECTOR_STORE(stxv, st_i64, 0)
+VSX_VECTOR_STORE(stxvx, st_i64, 1)
#ifdef TARGET_PPC64
#define VSX_VECTOR_LOAD_STORE_LENGTH(name) \
@@ -329,7 +378,6 @@ static void gen_##name(DisasContext *ctx)
\
return; \
} \
xth = tcg_temp_new_i64(); \
- get_cpu_vsrh(xth, rD(ctx->opcode) + 32); \
gen_set_access_type(ctx, ACCESS_INT); \
EA = tcg_temp_new(); \
gen_addr_imm_index(ctx, EA, 0x03); \
@@ -513,8 +561,8 @@ static void gen_##name(DisasContext *ctx)
\
tcg_temp_free_i64(xth); \
}
-VSX_LOAD_SCALAR_DS(stxsd, st64_i64)
-VSX_LOAD_SCALAR_DS(stxssp, st32fs)
+VSX_STORE_SCALAR_DS(stxsd, st64_i64)
+VSX_STORE_SCALAR_DS(stxssp, st32fs)
static void gen_mfvsrwz(DisasContext *ctx)
{
--
2.21.0
- [Qemu-ppc] [PULL 15/38] spapr/xive: print out the EQ page address in the monitor, (continued)
- [Qemu-ppc] [PULL 15/38] spapr/xive: print out the EQ page address in the monitor, David Gibson, 2019/05/22
- [Qemu-ppc] [PULL 10/38] target/ppc: Fix vslv and vsrv, David Gibson, 2019/05/22
- [Qemu-ppc] [PULL 09/38] target/ppc: Fix xxbrq, xxbrw, David Gibson, 2019/05/22
- [Qemu-ppc] [PULL 08/38] target/ppc: Fix xvxsigdp, David Gibson, 2019/05/22
- [Qemu-ppc] [PULL 33/38] spapr: check for the activation of the KVM IRQ device, David Gibson, 2019/05/22
- [Qemu-ppc] [PULL 16/38] Fix typo on "info pic" monitor cmd output for xive, David Gibson, 2019/05/22
- [Qemu-ppc] [PULL 21/38] spapr: Add forgotten capability to migration stream, David Gibson, 2019/05/22
- [Qemu-ppc] [PULL 17/38] target/ppc: Optimise VSX_LOAD_SCALAR_DS and VSX_VECTOR_LOAD_STORE,
David Gibson <=
- [Qemu-ppc] [PULL 14/38] spapr/xive: fix EQ page addresses above 64GB, David Gibson, 2019/05/22
- [Qemu-ppc] [PULL 28/38] spapr/xive: introduce a VM state change handler, David Gibson, 2019/05/22
- [Qemu-ppc] [PULL 24/38] spapr: Print out extra hints when CAS negotiation of interrupt mode fails, David Gibson, 2019/05/22
- [Qemu-ppc] [PULL 13/38] spapr/xive: EQ page should be naturally aligned, David Gibson, 2019/05/22
- [Qemu-ppc] [PULL 12/38] target/ppc: Fix xxspltib, David Gibson, 2019/05/22
- [Qemu-ppc] [PULL 31/38] sysbus: add a sysbus_mmio_unmap() helper, David Gibson, 2019/05/22
- [Qemu-ppc] [PULL 19/38] spapr/xive: Sanity checks of OV5 during CAS, David Gibson, 2019/05/22
- [Qemu-ppc] [PULL 20/38] target/ppc: Set PSSCR_EC on cpu halt to prevent spurious wakeup, David Gibson, 2019/05/22
- [Qemu-ppc] [PULL 22/38] target/ppc: Use vector variable shifts for VSL, VSR, VSRA, David Gibson, 2019/05/22
- [Qemu-ppc] [PULL 18/38] target/ppc: Fix xvabs[sd]p, xvnabs[sd]p, xvneg[sd]p, xvcpsgn[sd]p, David Gibson, 2019/05/22