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[Qemu-ppc] [PATCH v2 13/15] target/ppc: decode target register in VSX_VE
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From: |
Mark Cave-Ayland |
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Subject: |
[Qemu-ppc] [PATCH v2 13/15] target/ppc: decode target register in VSX_VECTOR_LOAD_STORE_LENGTH at translation time |
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Date: |
Sun, 2 Jun 2019 12:09:01 +0100 |
Signed-off-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target/ppc/helper.h | 8 +++----
target/ppc/mem_helper.c | 6 ++---
target/ppc/translate/vsx-impl.inc.c | 47 +++++++++++++++++++------------------
3 files changed, 30 insertions(+), 31 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index a5e12a3933..7ed9effff2 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -279,10 +279,10 @@ DEF_HELPER_3(stvebx, void, env, avr, tl)
DEF_HELPER_3(stvehx, void, env, avr, tl)
DEF_HELPER_3(stvewx, void, env, avr, tl)
#if defined(TARGET_PPC64)
-DEF_HELPER_4(lxvl, void, env, tl, tl, tl)
-DEF_HELPER_4(lxvll, void, env, tl, tl, tl)
-DEF_HELPER_4(stxvl, void, env, tl, tl, tl)
-DEF_HELPER_4(stxvll, void, env, tl, tl, tl)
+DEF_HELPER_4(lxvl, void, env, tl, vsr, tl)
+DEF_HELPER_4(lxvll, void, env, tl, vsr, tl)
+DEF_HELPER_4(stxvl, void, env, tl, vsr, tl)
+DEF_HELPER_4(stxvll, void, env, tl, vsr, tl)
#endif
DEF_HELPER_4(vsumsws, void, env, avr, avr, avr)
DEF_HELPER_4(vsum2sws, void, env, avr, avr, avr)
diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c
index 17a3c931a9..c533f88dc1 100644
--- a/target/ppc/mem_helper.c
+++ b/target/ppc/mem_helper.c
@@ -415,9 +415,8 @@ STVE(stvewx, cpu_stl_data_ra, bswap32, u32)
#define VSX_LXVL(name, lj) \
void helper_##name(CPUPPCState *env, target_ulong addr, \
- target_ulong xt_num, target_ulong rb) \
+ ppc_vsr_t *xt, target_ulong rb) \
{ \
- ppc_vsr_t *xt = &env->vsr[xt_num]; \
ppc_vsr_t t; \
uint64_t nb = GET_NB(rb); \
int i; \
@@ -446,9 +445,8 @@ VSX_LXVL(lxvll, 1)
#define VSX_STXVL(name, lj) \
void helper_##name(CPUPPCState *env, target_ulong addr, \
- target_ulong xt_num, target_ulong rb) \
+ ppc_vsr_t *xt, target_ulong rb) \
{ \
- ppc_vsr_t *xt = &env->vsr[xt_num]; \
ppc_vsr_t t = *xt; \
target_ulong nb = GET_NB(rb); \
int i; \
diff --git a/target/ppc/translate/vsx-impl.inc.c
b/target/ppc/translate/vsx-impl.inc.c
index e05756b8c1..931c7c33ac 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -343,29 +343,30 @@ VSX_VECTOR_STORE(stxv, st_i64, 0)
VSX_VECTOR_STORE(stxvx, st_i64, 1)
#ifdef TARGET_PPC64
-#define VSX_VECTOR_LOAD_STORE_LENGTH(name) \
-static void gen_##name(DisasContext *ctx) \
-{ \
- TCGv EA, xt; \
- \
- if (xT(ctx->opcode) < 32) { \
- if (unlikely(!ctx->vsx_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VSXU); \
- return; \
- } \
- } else { \
- if (unlikely(!ctx->altivec_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VPU); \
- return; \
- } \
- } \
- EA = tcg_temp_new(); \
- xt = tcg_const_tl(xT(ctx->opcode)); \
- gen_set_access_type(ctx, ACCESS_INT); \
- gen_addr_register(ctx, EA); \
- gen_helper_##name(cpu_env, EA, xt, cpu_gpr[rB(ctx->opcode)]); \
- tcg_temp_free(EA); \
- tcg_temp_free(xt); \
+#define VSX_VECTOR_LOAD_STORE_LENGTH(name) \
+static void gen_##name(DisasContext *ctx) \
+{ \
+ TCGv EA; \
+ TCGv_ptr xt; \
+ \
+ if (xT(ctx->opcode) < 32) { \
+ if (unlikely(!ctx->vsx_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VSXU); \
+ return; \
+ } \
+ } else { \
+ if (unlikely(!ctx->altivec_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VPU); \
+ return; \
+ } \
+ } \
+ EA = tcg_temp_new(); \
+ xt = gen_vsr_ptr(xT(ctx->opcode)); \
+ gen_set_access_type(ctx, ACCESS_INT); \
+ gen_addr_register(ctx, EA); \
+ gen_helper_##name(cpu_env, EA, xt, cpu_gpr[rB(ctx->opcode)]); \
+ tcg_temp_free(EA); \
+ tcg_temp_free_ptr(xt); \
}
VSX_VECTOR_LOAD_STORE_LENGTH(lxvl)
--
2.11.0
- Re: [Qemu-ppc] [Qemu-devel] [PATCH v2 09/15] target/ppc: introduce GEN_VSX_HELPER_X1 macro to fpu_helper.c, (continued)
- [Qemu-ppc] [PATCH v2 08/15] target/ppc: introduce GEN_VSX_HELPER_X2_AB macro to fpu_helper.c, Mark Cave-Ayland, 2019/06/02
- [Qemu-ppc] [PATCH v2 05/15] target/ppc: introduce GEN_VSX_HELPER_X3 macro to fpu_helper.c, Mark Cave-Ayland, 2019/06/02
- [Qemu-ppc] [PATCH v2 07/15] target/ppc: introduce GEN_VSX_HELPER_X2 macro to fpu_helper.c, Mark Cave-Ayland, 2019/06/02
- [Qemu-ppc] [PATCH v2 01/15] target/ppc: remove getVSR()/putVSR() from fpu_helper.c, Mark Cave-Ayland, 2019/06/02
- [Qemu-ppc] [PATCH v2 13/15] target/ppc: decode target register in VSX_VECTOR_LOAD_STORE_LENGTH at translation time,
Mark Cave-Ayland <=
- [Qemu-ppc] [PATCH v2 10/15] target/ppc: introduce GEN_VSX_HELPER_R3 macro to fpu_helper.c, Mark Cave-Ayland, 2019/06/02
- [Qemu-ppc] [PATCH v2 11/15] target/ppc: introduce GEN_VSX_HELPER_R2 macro to fpu_helper.c, Mark Cave-Ayland, 2019/06/02
- [Qemu-ppc] [PATCH v2 14/15] target/ppc: decode target register in VSX_EXTRACT_INSERT at translation time, Mark Cave-Ayland, 2019/06/02
- [Qemu-ppc] [PATCH v2 12/15] target/ppc: introduce GEN_VSX_HELPER_R2_AB macro to fpu_helper.c, Mark Cave-Ayland, 2019/06/02
- [Qemu-ppc] [PATCH v2 15/15] target/ppc: improve VSX_FMADD with new GEN_VSX_HELPER_VSX_MADD macro, Mark Cave-Ayland, 2019/06/02
- Re: [Qemu-ppc] [Qemu-devel] [PATCH v2 00/15] target/ppc: remove getVSR()/putVSR() and further tidy-up, no-reply, 2019/06/04