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Re: [PATCH 7/9] ppc/pnv: Add POWER10 quads
From: |
Greg Kurz |
Subject: |
Re: [PATCH 7/9] ppc/pnv: Add POWER10 quads |
Date: |
Wed, 20 May 2020 16:44:45 +0200 |
On Wed, 13 May 2020 17:11:07 +0200
Cédric Le Goater <address@hidden> wrote:
> Still needs some refinements on the XSCOM registers.
>
> Signed-off-by: Cédric Le Goater <address@hidden>
> ---
> include/hw/ppc/pnv.h | 4 ++++
> hw/ppc/pnv.c | 33 +++++++++++++++++++++++++++++++++
> 2 files changed, 37 insertions(+)
>
> diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
> index 3ff610a9c7b5..86bfa2107a8c 100644
> --- a/include/hw/ppc/pnv.h
> +++ b/include/hw/ppc/pnv.h
> @@ -123,6 +123,10 @@ typedef struct Pnv10Chip {
> Pnv9Psi psi;
> PnvLpcController lpc;
> PnvOCC occ;
> +
> + uint32_t nr_quads;
> + PnvQuad *quads;
> +
> } Pnv10Chip;
>
> #define PNV10_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf)
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index 9f1698a74467..fc751dd575d4 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -1621,6 +1621,33 @@ static void pnv_chip_power10_instance_init(Object *obj)
> TYPE_PNV10_OCC, &error_abort, NULL);
> }
>
> +
> +static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp)
> +{
> + PnvChip *chip = PNV_CHIP(chip10);
> + int i;
> +
> + chip10->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4);
> + chip10->quads = g_new0(PnvQuad, chip10->nr_quads);
> +
> + for (i = 0; i < chip10->nr_quads; i++) {
> + char eq_name[32];
> + PnvQuad *eq = &chip10->quads[i];
> + PnvCore *pnv_core = chip->cores[i * 4];
> + int core_id = CPU_CORE(pnv_core)->core_id;
> +
> + snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id);
> + object_initialize_child(OBJECT(chip), eq_name, eq, sizeof(*eq),
> + TYPE_PNV_QUAD, &error_fatal, NULL);
> +
> + object_property_set_int(OBJECT(eq), core_id, "id", &error_fatal);
> + object_property_set_bool(OBJECT(eq), true, "realized", &error_fatal);
> +
> + pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->id),
> + &eq->xscom_regs);
> + }
> +}
So, this function is mostly identical to the P9 variant, except the xscom
offset. Unless the refinements envisioned in the changelog bring substantial
change, I'd suggest to move this to a common helper and call it from dedicated
P9 and P10 realize functions.
> +
> static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
> {
> PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
> @@ -1642,6 +1669,12 @@ static void pnv_chip_power10_realize(DeviceState *dev,
> Error **errp)
> return;
> }
>
> + pnv_chip_power10_quad_realize(chip10, &local_err);
> + if (local_err) {
> + error_propagate(errp, local_err);
> + return;
> + }
> +
> /* XIVE2 interrupt controller (POWER10) */
> object_property_set_int(OBJECT(&chip10->xive), PNV10_XIVE2_IC_BASE(chip),
> "ic-bar", &error_fatal);
- Re: [PATCH 4/9] ppc/xive2: Introduce a presenter matching routine, (continued)
- [PATCH 5/9] ppc/pnv: Add a XIVE2 controller to the POWER10 chip., Cédric Le Goater, 2020/05/13
- [PATCH 6/9] ppc/pnv: Add a OCC model for POWER10, Cédric Le Goater, 2020/05/13
- [PATCH 7/9] ppc/pnv: Add POWER10 quads, Cédric Le Goater, 2020/05/13
- Re: [PATCH 7/9] ppc/pnv: Add POWER10 quads,
Greg Kurz <=
- [PATCH 8/9] ppc/pnv: Add model for POWER9 PHB5 PCIe Host bridge, Cédric Le Goater, 2020/05/13
- [PATCH 9/9] ppc/psi: Add support for StoreEOI and 64k ESB pages (POWER10), Cédric Le Goater, 2020/05/13
- Re: [PATCH 0/9] ppc/pnv: Introduce the XIVE2 and PHB5 controllers for the POWER10 chip, Greg Kurz, 2020/05/19