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[PULL 06/40] target/ppc: add vmulld instruction
From: |
David Gibson |
Subject: |
[PULL 06/40] target/ppc: add vmulld instruction |
Date: |
Tue, 18 Aug 2020 14:18:48 +1000 |
From: Lijun Pan <ljp@linux.ibm.com>
vmulld: Vector Multiply Low Doubleword.
Signed-off-by: Lijun Pan <ljp@linux.ibm.com>
Message-Id: <20200701234344.91843-6-ljp@linux.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/translate/vmx-impl.inc.c | 1 +
target/ppc/translate/vmx-ops.inc.c | 4 ++++
2 files changed, 5 insertions(+)
diff --git a/target/ppc/translate/vmx-impl.inc.c
b/target/ppc/translate/vmx-impl.inc.c
index b6c9290707..f8e8b978ec 100644
--- a/target/ppc/translate/vmx-impl.inc.c
+++ b/target/ppc/translate/vmx-impl.inc.c
@@ -807,6 +807,7 @@ GEN_VXFORM_DUAL(vmulouw, PPC_ALTIVEC, PPC_NONE,
GEN_VXFORM(vmulosb, 4, 4);
GEN_VXFORM(vmulosh, 4, 5);
GEN_VXFORM(vmulosw, 4, 6);
+GEN_VXFORM_V(vmulld, MO_64, tcg_gen_gvec_mul, 4, 7);
GEN_VXFORM(vmuleub, 4, 8);
GEN_VXFORM(vmuleuh, 4, 9);
GEN_VXFORM(vmuleuw, 4, 10);
diff --git a/target/ppc/translate/vmx-ops.inc.c
b/target/ppc/translate/vmx-ops.inc.c
index 84e05fb827..b49787ac97 100644
--- a/target/ppc/translate/vmx-ops.inc.c
+++ b/target/ppc/translate/vmx-ops.inc.c
@@ -48,6 +48,9 @@ GEN_HANDLER_E(name, 0x04, opc2, opc3, inval, PPC_NONE,
PPC2_ISA300)
GEN_HANDLER_E_2(name, 0x04, opc2, opc3, opc4, 0x00000000, PPC_NONE, \
PPC2_ISA300)
+#define GEN_VXFORM_310(name, opc2, opc3) \
+GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ISA310)
+
#define GEN_VXFORM_DUAL(name0, name1, opc2, opc3, type0, type1) \
GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, type0, type1)
@@ -104,6 +107,7 @@ GEN_VXFORM_DUAL(vmulouw, vmuluwm, 4, 2, PPC_ALTIVEC,
PPC_NONE),
GEN_VXFORM(vmulosb, 4, 4),
GEN_VXFORM(vmulosh, 4, 5),
GEN_VXFORM_207(vmulosw, 4, 6),
+GEN_VXFORM_310(vmulld, 4, 7),
GEN_VXFORM(vmuleub, 4, 8),
GEN_VXFORM(vmuleuh, 4, 9),
GEN_VXFORM_207(vmuleuw, 4, 10),
--
2.26.2
- [PULL 00/40] ppc-for-5.2 queue 20200818, David Gibson, 2020/08/18
- [PULL 01/40] target/ppc: Fix TCG leak with the evmwsmiaa instruction, David Gibson, 2020/08/18
- [PULL 04/40] target/ppc: add byte-reverse br[dwh] instructions, David Gibson, 2020/08/18
- [PULL 02/40] target/ppc: Introduce Power ISA 3.1 flag, David Gibson, 2020/08/18
- [PULL 03/40] target/ppc: Enable Power ISA 3.1, David Gibson, 2020/08/18
- [PULL 06/40] target/ppc: add vmulld instruction,
David Gibson <=
- [PULL 08/40] spapr: Use error_append_hint() in spapr_caps.c, David Gibson, 2020/08/18
- [PULL 05/40] target/ppc: convert vmuluwm to tcg_gen_gvec_mul, David Gibson, 2020/08/18
- [PULL 09/40] spapr: Forbid nested KVM-HV in pre-power9 compat mode, David Gibson, 2020/08/18
- [PULL 11/40] Update PowerPC AT_HWCAP2 definition, David Gibson, 2020/08/18
- [PULL 10/40] ppc/xive: Fix some typos in comments, David Gibson, 2020/08/18
- [PULL 13/40] target/ppc: add vmulh{su}w instructions, David Gibson, 2020/08/18
- [PULL 14/40] target/ppc: add vmulh{su}d instructions, David Gibson, 2020/08/18
- [PULL 16/40] docs: adding NUMA documentation for pseries, David Gibson, 2020/08/18
- [PULL 12/40] target/ppc: add vmulld to INDEX_op_mul_vec case, David Gibson, 2020/08/18
- [PULL 07/40] ppc/spapr: Fix 32 bit logical memory block size assumptions, David Gibson, 2020/08/18