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Re: [PATCH 2/7] target/ppc: Add support for prefixed load/store instruct
From: |
Gustavo Romero |
Subject: |
Re: [PATCH 2/7] target/ppc: Add support for prefixed load/store instructions |
Date: |
Fri, 9 Oct 2020 13:26:16 -0300 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 |
Hi David,
On 10/8/20 10:45 PM, Paul A. Clarke wrote:
On Fri, Oct 09, 2020 at 11:50:10AM +1100, David Gibson wrote:
On Mon, Oct 05, 2020 at 01:03:14AM -0300, Gustavo Romero wrote:
From: Michael Roth <mdroth@linux.vnet.ibm.com>
This commit adds support for the following prefixed load and store
instructions for GPRs:
plbz, plh{a,z}, plw{a,z}, pld, plq
pstb, psth, pstw, pstd, pstq
paddi
Are there architecture docs publically available yet which describe
these instructions?
Are you looking for the ISA? The "Power ISA Version 3.1" can be found
at https://www-355.ibm.com/systems/power/openpower/, under "Public
Documents" (POWER10 ISA), or directly at this horrible link:
https://ibm.box.com/s/hhjfw0x0lrbtyzmiaffnbxh2fuo0fog0
As Paul pointed out (thanks Paul!) - and provided links for, you can check
the added instructions by that patch series in Power ISA v3.1. I think the
first interesting bits in ISA v3.1 for that series would be the following:
1.6 Instruction Formats, p. 11.
For those not aware, there is a bold black marker at left of every new text
in comparison with the immediately previous ISA version (v3.0), which works
like a "diff" for the ISA text, so the marks can be helpful for locating a
new text regarding prefixed instructions (prefixed instructions were
introduced in v3.1) in sections like 1.6, which also contains old text.
Secondly:
1.6.3 Instruction Prefix Formats, p. 22,
which will describe most of what is addressed in 1/7 for adding the
prefixed insns infrastructure.
Then one can find more information about the new added instructions, like
plbz, VSX-related, and FP-related ones in:
3.3.2 Fixed-Point Load Instructions, p. 51
4.6.2 Floating-Point Load Instructions, p. 149
There is also new text scattered all over Chapter 7 Interrupts, p. 1247,
mostly because there are new SRR bits to inform if an exception or interrupt
was caused by a prefixed instruction. In that case the thick bold marks
(marking new text) might help to find the new parts.
I'll add these references to v2.
HTH.
Thanks,
Gustavo
- [PATCH 1/7] target/ppc: Add infrastructure for prefixed instructions, Gustavo Romero, 2020/10/05
- [PATCH 3/7] tests/tcg: Add tests for prefixed load/store instructions, Gustavo Romero, 2020/10/05
- [PATCH 4/7] target/ppc: Add support for paired vector load/store instructions, Gustavo Romero, 2020/10/05
- [PATCH 5/7] tests/tcg: Add tests for paired vector load/store instructions, Gustavo Romero, 2020/10/05
- [PATCH 6/7] target/ppc: Add support for prefixed load/store FP instructions, Gustavo Romero, 2020/10/05
- [PATCH 7/7] tests/tcg: Add tests for prefixed load/store FP instructions, Gustavo Romero, 2020/10/05
- Re: [PATCH 1/7] target/ppc: Add infrastructure for prefixed instructions, David Gibson, 2020/10/08