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[PULL 00/18] ppc-for-6.2 queue 20210827
From: |
David Gibson |
Subject: |
[PULL 00/18] ppc-for-6.2 queue 20210827 |
Date: |
Fri, 27 Aug 2021 17:09:28 +1000 |
The following changes since commit f214d8e0150766c31172e16ef4b17674f549d852:
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210826'
into staging (2021-08-26 18:03:57 +0100)
are available in the Git repository at:
https://gitlab.com/dgibson/qemu.git tags/ppc-for-6.2-20210827
for you to fetch changes up to 0ff16b6b78831240c39cfaaeab1f22ae52c84b09:
target/ppc: fix vector registers access in gdbstub for little-endian
(2021-08-27 12:43:13 +1000)
----------------------------------------------------------------
ppc patch queue 2021-08-27
First ppc pull request for qemu-6.2. As usual, there's a fair bit
here, since it's been queued during the 6.1 freeze. Highlights are:
* Some fixes for 128 bit arithmetic and some vector opcodes that use
them
* Significant improvements to the powernv to support POWER10 cpus
(more to come though)
* Several cleanups to the ppc softmmu code
* A few other assorted fixes
----------------------------------------------------------------
Cédric Le Goater (10):
xive: Remove extra '0x' prefix in trace events
ppc/pnv: update skiboot to commit 820d43c0a775.
ppc: Add a POWER10 DD2 CPU
ppc/pnv: Change the POWER10 machine to support DD2 only
ppc/pnv: powerpc_excp: Do not discard HDECR exception when entering
power-saving mode
ppc/pnv: Use a simple incrementing index for the chip-id
ppc/pnv: Distribute RAM among the chips
ppc/pnv: add a chip topology index for POWER10
ppc/xive: Export PQ get/set routines
ppc/xive: Export xive_presenter_notify()
David Gibson (1):
spapr_pci: Fix leak in spapr_phb_vfio_get_loc_code() with g_autofree
Lucas Mateus Castro (alqotel) (3):
target/ppc: divided mmu_helper.c in 2 files
target/ppc: moved ppc_store_sdr1 to mmu_common.c
target/ppc: moved store_40x_sler to helper_regs.c
Matheus Ferst (4):
include/qemu/int128.h: define struct Int128 according to the host
endianness
target/ppc: fix vextu[bhw][lr]x helpers
include/qemu/int128.h: introduce bswap128s
target/ppc: fix vector registers access in gdbstub for little-endian
hw/intc/spapr_xive_kvm.c | 8 +-
hw/intc/trace-events | 10 +-
hw/intc/xive.c | 14 +-
hw/ppc/pnv.c | 46 +-
hw/ppc/pnv_core.c | 2 +-
hw/ppc/pnv_xscom.c | 2 +
hw/ppc/spapr_pci.c | 22 +-
include/hw/ppc/pnv.h | 35 +-
include/hw/ppc/xive.h | 8 +
include/qemu/int128.h | 44 +-
pc-bios/skiboot.lid | Bin 1667280 -> 2528128 bytes
roms/skiboot | 2 +-
target/ppc/cpu-models.c | 4 +-
target/ppc/cpu-models.h | 1 +
target/ppc/cpu.c | 28 -
target/ppc/cpu.h | 9 +
target/ppc/cpu_init.c | 3 +
target/ppc/excp_helper.c | 6 -
target/ppc/gdbstub.c | 32 +-
target/ppc/helper_regs.c | 12 +
target/ppc/int_helper.c | 38 +-
target/ppc/internal.h | 39 ++
target/ppc/meson.build | 8 +-
target/ppc/mmu_common.c | 1620 ++++++++++++++++++++++++++++++++++++++++++++++
target/ppc/mmu_helper.c | 1590 +--------------------------------------------
25 files changed, 1823 insertions(+), 1760 deletions(-)
create mode 100644 target/ppc/mmu_common.c
- [PULL 00/18] ppc-for-6.2 queue 20210827,
David Gibson <=
- [PULL 02/18] spapr_pci: Fix leak in spapr_phb_vfio_get_loc_code() with g_autofree, David Gibson, 2021/08/27
- [PULL 01/18] xive: Remove extra '0x' prefix in trace events, David Gibson, 2021/08/27
- [PULL 04/18] target/ppc: moved ppc_store_sdr1 to mmu_common.c, David Gibson, 2021/08/27
- [PULL 03/18] target/ppc: divided mmu_helper.c in 2 files, David Gibson, 2021/08/27
- [PULL 05/18] target/ppc: moved store_40x_sler to helper_regs.c, David Gibson, 2021/08/27
- [PULL 09/18] ppc/pnv: powerpc_excp: Do not discard HDECR exception when entering power-saving mode, David Gibson, 2021/08/27
- [PULL 07/18] ppc: Add a POWER10 DD2 CPU, David Gibson, 2021/08/27
- [PULL 08/18] ppc/pnv: Change the POWER10 machine to support DD2 only, David Gibson, 2021/08/27
- [PULL 10/18] ppc/pnv: Use a simple incrementing index for the chip-id, David Gibson, 2021/08/27
- [PULL 13/18] ppc/xive: Export PQ get/set routines, David Gibson, 2021/08/27