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[PATCH v2 17/21] target/ppc: Remove msr_fe0 and msr_fe1 macros
From: |
Víctor Colombo |
Subject: |
[PATCH v2 17/21] target/ppc: Remove msr_fe0 and msr_fe1 macros |
Date: |
Mon, 2 May 2022 11:39:30 -0300 |
msr_fe0 and msr_fe1 macros hide the usage of env->msr, which is a bad
behavior. Substitute it with FIELD_EX64 calls that explicitly use
env->msr as a parameter.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
---
v2: Remove M_MSR_FE* and use FIELD_EX64 instead. As the bit numbers
for FE0 and FE1 are not continuous, we can't benefit from a unified
FIELD for them :(
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
---
target/ppc/cpu.h | 5 +++--
target/ppc/excp_helper.c | 18 ++++++++++++------
2 files changed, 15 insertions(+), 8 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 9683e6a359..5fce8f00da 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -363,6 +363,9 @@ FIELD(MSR, EE, MSR_EE, 1)
FIELD(MSR, PR, MSR_PR, 1)
FIELD(MSR, FP, MSR_FP, 1)
FIELD(MSR, ME, MSR_ME, 1)
+/* MSR_FE0 and MSR_FE1 are not side-by-side so we can't combine them */
+FIELD(MSR, FE0, MSR_FE0, 1)
+FIELD(MSR, FE1, MSR_FE1, 1)
FIELD(MSR, EP, MSR_EP, 1)
FIELD(MSR, IR, MSR_IR, 1)
FIELD(MSR, DR, MSR_DR, 1)
@@ -484,8 +487,6 @@ FIELD(MSR, LE, MSR_LE, 1)
#else
#define msr_hv (0)
#endif
-#define msr_fe0 ((env->msr >> MSR_FE0) & 1)
-#define msr_fe1 ((env->msr >> MSR_FE1) & 1)
#define msr_ts ((env->msr >> MSR_TS1) & 3)
#define DBCR0_ICMP (1 << 27)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 30baad0489..549b86cf0b 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -478,7 +478,8 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_PROGRAM: /* Program exception */
switch (env->error_code & ~0xF) {
case POWERPC_EXCP_FP:
- if ((msr_fe0 == 0 && msr_fe1 == 0) ||
+ if ((!FIELD_EX64(env->msr, MSR, FE0) &&
+ !FIELD_EX64(env->msr, MSR, FE1)) ||
!FIELD_EX64(env->msr, MSR, FP)) {
trace_ppc_excp_fp_ignore();
powerpc_reset_excp_state(cpu);
@@ -616,7 +617,8 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_PROGRAM: /* Program exception */
switch (env->error_code & ~0xF) {
case POWERPC_EXCP_FP:
- if ((msr_fe0 == 0 && msr_fe1 == 0) ||
+ if ((!FIELD_EX64(env->msr, MSR, FE0) &&
+ !FIELD_EX64(env->msr, MSR, FE1)) ||
!FIELD_EX64(env->msr, MSR, FP)) {
trace_ppc_excp_fp_ignore();
powerpc_reset_excp_state(cpu);
@@ -790,7 +792,8 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_PROGRAM: /* Program exception */
switch (env->error_code & ~0xF) {
case POWERPC_EXCP_FP:
- if ((msr_fe0 == 0 && msr_fe1 == 0) ||
+ if ((!FIELD_EX64(env->msr, MSR, FE0) &&
+ !FIELD_EX64(env->msr, MSR, FE1)) ||
!FIELD_EX64(env->msr, MSR, FP)) {
trace_ppc_excp_fp_ignore();
powerpc_reset_excp_state(cpu);
@@ -976,7 +979,8 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_PROGRAM: /* Program exception */
switch (env->error_code & ~0xF) {
case POWERPC_EXCP_FP:
- if ((msr_fe0 == 0 && msr_fe1 == 0) ||
+ if ((!FIELD_EX64(env->msr, MSR, FE0) &&
+ !FIELD_EX64(env->msr, MSR, FE1)) ||
!FIELD_EX64(env->msr, MSR, FP)) {
trace_ppc_excp_fp_ignore();
powerpc_reset_excp_state(cpu);
@@ -1175,7 +1179,8 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_PROGRAM: /* Program exception */
switch (env->error_code & ~0xF) {
case POWERPC_EXCP_FP:
- if ((msr_fe0 == 0 && msr_fe1 == 0) ||
+ if ((!FIELD_EX64(env->msr, MSR, FE0) &&
+ !FIELD_EX64(env->msr, MSR, FE1)) ||
!FIELD_EX64(env->msr, MSR, FP)) {
trace_ppc_excp_fp_ignore();
powerpc_reset_excp_state(cpu);
@@ -1439,7 +1444,8 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_PROGRAM: /* Program exception */
switch (env->error_code & ~0xF) {
case POWERPC_EXCP_FP:
- if ((msr_fe0 == 0 && msr_fe1 == 0) ||
+ if ((!FIELD_EX64(env->msr, MSR, FE0) &&
+ !FIELD_EX64(env->msr, MSR, FE1)) ||
!FIELD_EX64(env->msr, MSR, FP)) {
trace_ppc_excp_fp_ignore();
powerpc_reset_excp_state(cpu);
--
2.25.1
- Re: [PATCH v2 11/21] target/ppc: Remove msr_gs macro, (continued)
- [PATCH v2 13/21] target/ppc: Remove msr_me macro, Víctor Colombo, 2022/05/02
- [PATCH v2 14/21] target/ppc: Remove msr_ir macro, Víctor Colombo, 2022/05/02
- [PATCH v2 15/21] target/ppc: Remove msr_dr macro, Víctor Colombo, 2022/05/02
- [PATCH v2 16/21] target/ppc: Remove msr_ep macro, Víctor Colombo, 2022/05/02
- [PATCH v2 17/21] target/ppc: Remove msr_fe0 and msr_fe1 macros,
Víctor Colombo <=
- [PATCH v2 18/21] target/ppc: Remove msr_ts macro, Víctor Colombo, 2022/05/02
- [PATCH v2 19/21] target/ppc: Remove msr_hv macro, Víctor Colombo, 2022/05/02
- [PATCH v2 20/21] target/ppc: Add unused msr bits FIELDs, Víctor Colombo, 2022/05/02
- [PATCH v2 21/21] target/ppc: Change MSR_* to follow POWER ISA numbering convention, Víctor Colombo, 2022/05/02
- Re: [PATCH v2 00/21] target/ppc: Remove hidden usages of *env, Cédric Le Goater, 2022/05/02