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[PULL 29/34] target/ppc: Implemented pmxvi*ger* instructions
From: |
Daniel Henrique Barboza |
Subject: |
[PULL 29/34] target/ppc: Implemented pmxvi*ger* instructions |
Date: |
Thu, 26 May 2022 18:38:10 -0300 |
From: "Lucas Mateus Castro (alqotel)" <lucas.araujo@eldorado.org.br>
Implement the following PowerISA v3.1 instructions:
pmxvi4ger8: Prefixed Masked VSX Vector 8-bit Signed/Unsigned Integer
GER (rank-4 update)
pmxvi4ger8pp: Prefixed Masked VSX Vector 8-bit Signed/Unsigned Integer
GER (rank-4 update) Positive multiply, Positive accumulate
pmxvi8ger4: Prefixed Masked VSX Vector 4-bit Signed Integer GER
(rank-8 update)
pmxvi8ger4pp: Prefixed Masked VSX Vector 4-bit Signed Integer GER
(rank-8 update) Positive multiply, Positive accumulate
pmxvi8ger4spp: Prefixed Masked VSX Vector 8-bit Signed/Unsigned Integer
GER (rank-4 update) with Saturate Positive multiply, Positive accumulate
pmxvi16ger2: Prefixed Masked VSX Vector 16-bit Signed Integer GER
(rank-2 update)
pmxvi16ger2pp: Prefixed Masked VSX Vector 16-bit Signed Integer GER
(rank-2 update) Positive multiply, Positive accumulate
pmxvi16ger2s: Prefixed Masked VSX Vector 16-bit Signed Integer GER
(rank-2 update) with Saturation
pmxvi16ger2spp: Prefixed Masked VSX Vector 16-bit Signed Integer GER
(rank-2 update) with Saturation Positive multiply, Positive accumulate
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220524140537.27451-4-lucas.araujo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
target/ppc/insn64.decode | 30 +++++++++++++++++++++++++++++
target/ppc/translate/vsx-impl.c.inc | 10 ++++++++++
2 files changed, 40 insertions(+)
diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
index 691e8fe6c0..0eed35c8cd 100644
--- a/target/ppc/insn64.decode
+++ b/target/ppc/insn64.decode
@@ -68,6 +68,15 @@
...... ..... ..... ..... ..... .. .... \
&8RR_XX4_uim3 xt=%8rr_xx_xt xa=%8rr_xx_xa xb=%8rr_xx_xb
xc=%8rr_xx_xc
+# Format MMIRR:XX3
+&MMIRR_XX3 !extern xa xb xt pmsk xmsk ymsk
+%xx3_xa 2:1 16:5
+%xx3_xb 1:1 11:5
+%xx3_at 23:3
+@MMIRR_XX3 ...... .. .... .. . . ........ xmsk:4 ymsk:4 \
+ ...... ... .. ..... ..... ........ ... \
+ &MMIRR_XX3 xa=%xx3_xa xb=%xx3_xb xt=%xx3_at
+
### Fixed-Point Load Instructions
PLBZ 000001 10 0--.-- .................. \
@@ -115,6 +124,27 @@ PSTFS 000001 10 0--.-- .................. \
PSTFD 000001 10 0--.-- .................. \
110110 ..... ..... ................ @PLS_D
+## VSX GER instruction
+
+PMXVI4GER8 000001 11 1001 -- - - pmsk:8 ........ \
+ 111011 ... -- ..... ..... 00100011 ..- @MMIRR_XX3
+PMXVI4GER8PP 000001 11 1001 -- - - pmsk:8 ........ \
+ 111011 ... -- ..... ..... 00100010 ..- @MMIRR_XX3
+PMXVI8GER4 000001 11 1001 -- - - pmsk:4 ---- ........ \
+ 111011 ... -- ..... ..... 00000011 ..- @MMIRR_XX3
+PMXVI8GER4PP 000001 11 1001 -- - - pmsk:4 ---- ........ \
+ 111011 ... -- ..... ..... 00000010 ..- @MMIRR_XX3
+PMXVI16GER2 000001 11 1001 -- - - pmsk:2 ------ ........ \
+ 111011 ... -- ..... ..... 01001011 ..- @MMIRR_XX3
+PMXVI16GER2PP 000001 11 1001 -- - - pmsk:2 ------ ........ \
+ 111011 ... -- ..... ..... 01101011 ..- @MMIRR_XX3
+PMXVI8GER4SPP 000001 11 1001 -- - - pmsk:4 ---- ........ \
+ 111011 ... -- ..... ..... 01100011 ..- @MMIRR_XX3
+PMXVI16GER2S 000001 11 1001 -- - - pmsk:2 ------ ........ \
+ 111011 ... -- ..... ..... 00101011 ..- @MMIRR_XX3
+PMXVI16GER2SPP 000001 11 1001 -- - - pmsk:2 ------ ........ \
+ 111011 ... -- ..... ..... 00101010 ..- @MMIRR_XX3
+
### Prefixed No-operation Instruction
@PNOP 000001 11 0000-- 000000000000000000 \
diff --git a/target/ppc/translate/vsx-impl.c.inc
b/target/ppc/translate/vsx-impl.c.inc
index 6026b203e0..b10eded1da 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -2888,6 +2888,16 @@ TRANS(XVI16GER2PP, do_ger, gen_helper_XVI16GER2PP)
TRANS(XVI16GER2S, do_ger, gen_helper_XVI16GER2S)
TRANS(XVI16GER2SPP, do_ger, gen_helper_XVI16GER2SPP)
+TRANS64(PMXVI4GER8, do_ger, gen_helper_XVI4GER8)
+TRANS64(PMXVI4GER8PP, do_ger, gen_helper_XVI4GER8PP)
+TRANS64(PMXVI8GER4, do_ger, gen_helper_XVI8GER4)
+TRANS64(PMXVI8GER4PP, do_ger, gen_helper_XVI8GER4PP)
+TRANS64(PMXVI8GER4SPP, do_ger, gen_helper_XVI8GER4SPP)
+TRANS64(PMXVI16GER2, do_ger, gen_helper_XVI16GER2)
+TRANS64(PMXVI16GER2PP, do_ger, gen_helper_XVI16GER2PP)
+TRANS64(PMXVI16GER2S, do_ger, gen_helper_XVI16GER2S)
+TRANS64(PMXVI16GER2SPP, do_ger, gen_helper_XVI16GER2SPP)
+
#undef GEN_XX2FORM
#undef GEN_XX3FORM
#undef GEN_XX2IFORM
--
2.36.1
- [PULL 25/34] tcg/ppc: Optimize memory ordering generation with lwsync, (continued)
- [PULL 25/34] tcg/ppc: Optimize memory ordering generation with lwsync, Daniel Henrique Barboza, 2022/05/26
- [PULL 17/34] target/ppc: declare xvxsigsp helper with call flags, Daniel Henrique Barboza, 2022/05/26
- [PULL 18/34] target/ppc: declare xxextractuw and xxinsertw helpers with call flags, Daniel Henrique Barboza, 2022/05/26
- [PULL 21/34] target/ppc: declare vmsumuh[ms] helper with call flags, Daniel Henrique Barboza, 2022/05/26
- [PULL 26/34] target/ppc: Implement lwsync with weaker memory ordering, Daniel Henrique Barboza, 2022/05/26
- [PULL 24/34] tcg/ppc: ST_ST memory ordering is not provided with eieio, Daniel Henrique Barboza, 2022/05/26
- [PULL 22/34] target/ppc: declare vmsumsh[ms] helper with call flags, Daniel Henrique Barboza, 2022/05/26
- [PULL 23/34] target/ppc: Fix eieio memory ordering semantics, Daniel Henrique Barboza, 2022/05/26
- [PULL 27/34] target/ppc: Implement xxm[tf]acc and xxsetaccz, Daniel Henrique Barboza, 2022/05/26
- [PULL 28/34] target/ppc: Implemented xvi*ger* instructions, Daniel Henrique Barboza, 2022/05/26
- [PULL 29/34] target/ppc: Implemented pmxvi*ger* instructions,
Daniel Henrique Barboza <=
- [PULL 30/34] target/ppc: Implemented xvf*ger*, Daniel Henrique Barboza, 2022/05/26
- [PULL 31/34] target/ppc: Implemented xvf16ger*, Daniel Henrique Barboza, 2022/05/26
- [PULL 32/34] target/ppc: Implemented pmxvf*ger*, Daniel Henrique Barboza, 2022/05/26
- [PULL 34/34] linux-user: Add PowerPC ISA 3.1 and MMA to hwcap, Daniel Henrique Barboza, 2022/05/26
- [PULL 33/34] target/ppc: Implemented [pm]xvbf16ger2*, Daniel Henrique Barboza, 2022/05/26
- Re: [PULL 00/34] ppc queue, Richard Henderson, 2022/05/27