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[PULL 10/15] target/ppc: fix vbpermd in big endian hosts
From: |
Daniel Henrique Barboza |
Subject: |
[PULL 10/15] target/ppc: fix vbpermd in big endian hosts |
Date: |
Tue, 21 Jun 2022 06:43:55 -0300 |
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
The extract64 arguments are not endian dependent as they are only used
for bitwise operations. The current behavior in little-endian hosts is
correct; since the indexes in VRB are in PowerISA-ordering, we should
always invert the value before calling extract64. Also, using the VsrD
macro, we can have a single EXTRACT_BIT definition for big and
little-endian with the correct behavior.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220601125355.1266165-1-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
target/ppc/int_helper.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 16357c0900..11871947bc 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -1413,14 +1413,13 @@ XXGENPCV(XXGENPCVDM, 8)
#define VBPERMQ_INDEX(avr, i) ((avr)->u8[(i)])
#define VBPERMD_INDEX(i) (i)
#define VBPERMQ_DW(index) (((index) & 0x40) != 0)
-#define EXTRACT_BIT(avr, i, index) (extract64((avr)->u64[i], index, 1))
#else
#define VBPERMQ_INDEX(avr, i) ((avr)->u8[15 - (i)])
#define VBPERMD_INDEX(i) (1 - i)
#define VBPERMQ_DW(index) (((index) & 0x40) == 0)
-#define EXTRACT_BIT(avr, i, index) \
- (extract64((avr)->u64[1 - i], 63 - index, 1))
#endif
+#define EXTRACT_BIT(avr, i, index) \
+ (extract64((avr)->VsrD(i), 63 - index, 1))
void helper_vbpermd(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
{
--
2.36.1
- [PULL 02/15] target/ppc: Implemented vector divide quadword, (continued)
- [PULL 02/15] target/ppc: Implemented vector divide quadword, Daniel Henrique Barboza, 2022/06/21
- [PULL 03/15] target/ppc: Implemented vector divide extended word, Daniel Henrique Barboza, 2022/06/21
- [PULL 04/15] host-utils: Implemented unsigned 256-by-128 division, Daniel Henrique Barboza, 2022/06/21
- [PULL 08/15] target/ppc: Implemented vector module quadword, Daniel Henrique Barboza, 2022/06/21
- [PULL 07/15] target/ppc: Implemented vector module word/doubleword, Daniel Henrique Barboza, 2022/06/21
- [PULL 11/15] pnv/xive2: Access direct mapped thread contexts from all chips, Daniel Henrique Barboza, 2022/06/21
- [PULL 06/15] target/ppc: Implemented remaining vector divide extended, Daniel Henrique Barboza, 2022/06/21
- [PULL 09/15] ppc: fix boot with sam460ex, Daniel Henrique Barboza, 2022/06/21
- [PULL 12/15] ppc/pnv: fix extra indent spaces with DEFINE_PROP*, Daniel Henrique Barboza, 2022/06/21
- [PULL 05/15] host-utils: Implemented signed 256-by-128 division, Daniel Henrique Barboza, 2022/06/21
- [PULL 10/15] target/ppc: fix vbpermd in big endian hosts,
Daniel Henrique Barboza <=
- [PULL 13/15] target/ppc: avoid int32 multiply overflow in int_helper.c, Daniel Henrique Barboza, 2022/06/21
- [PULL 15/15] target/ppc: cpu_init: Clean up stop state on cpu reset, Daniel Henrique Barboza, 2022/06/21
- [PULL 14/15] target/ppc: fix unreachable code in fpu_helper.c, Daniel Henrique Barboza, 2022/06/21
- Re: [PULL 00/15] ppc queue, Richard Henderson, 2022/06/21