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[PATCH v6 14/33] hw/isa/piix3: Create USB controller in host device
From: |
Bernhard Beschow |
Subject: |
[PATCH v6 14/33] hw/isa/piix3: Create USB controller in host device |
Date: |
Mon, 9 Jan 2023 18:23:27 +0100 |
The USB controller is an integral part of PIIX3 (function 2). So create
it as part of the south bridge.
Note that the USB function is optional in QEMU. This is why it gets
object_initialize_child()'ed in realize rather than in instance_init.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20221022150508.26830-13-shentey@gmail.com>
---
include/hw/southbridge/piix.h | 4 ++++
hw/i386/pc_piix.c | 7 ++-----
hw/isa/piix3.c | 17 +++++++++++++++++
hw/isa/Kconfig | 1 +
4 files changed, 24 insertions(+), 5 deletions(-)
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
index b06d26fa11..762709f2fd 100644
--- a/include/hw/southbridge/piix.h
+++ b/include/hw/southbridge/piix.h
@@ -15,6 +15,7 @@
#include "hw/pci/pci_device.h"
#include "qom/object.h"
#include "hw/rtc/mc146818rtc.h"
+#include "hw/usb/hcd-uhci.h"
/* PIRQRC[A:D]: PIRQx Route Control Registers */
#define PIIX_PIRQCA 0x60
@@ -54,12 +55,15 @@ struct PIIXState {
int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
RTCState rtc;
+ UHCIState uhci;
/* Reset Control Register contents */
uint8_t rcr;
/* IO memory region for Reset Control Register (PIIX_RCR_IOPORT) */
MemoryRegion rcr_mem;
+
+ bool has_usb;
};
typedef struct PIIXState PIIX3State;
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 37afc01d30..61d8152078 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -52,7 +52,6 @@
#include "exec/memory.h"
#include "hw/acpi/acpi.h"
#include "hw/acpi/piix4.h"
-#include "hw/usb/hcd-uhci.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "sysemu/xen.h"
@@ -236,6 +235,8 @@ static void pc_init1(MachineState *machine,
pcms->bus = pci_bus;
pci_dev = pci_new_multifunction(-1, true, type);
+ object_property_set_bool(OBJECT(pci_dev), "has-usb",
+ machine_usb(machine), &error_abort);
pci_realize_and_unref(pci_dev, pci_bus, &error_fatal);
piix3 = PIIX3_PCI_DEVICE(pci_dev);
piix3->pic = x86ms->gsi;
@@ -314,10 +315,6 @@ static void pc_init1(MachineState *machine,
}
#endif
- if (pcmc->pci_enabled && machine_usb(machine)) {
- pci_create_simple(pci_bus, piix3_devfn + 2, TYPE_PIIX3_USB_UHCI);
- }
-
if (pcmc->pci_enabled && x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) {
PCIDevice *piix4_pm;
diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c
index e8ddb6a602..45c20dea17 100644
--- a/hw/isa/piix3.c
+++ b/hw/isa/piix3.c
@@ -288,6 +288,7 @@ static const MemoryRegionOps rcr_ops = {
static void pci_piix3_realize(PCIDevice *dev, Error **errp)
{
PIIX3State *d = PIIX3_PCI_DEVICE(dev);
+ PCIBus *pci_bus = pci_get_bus(dev);
ISABus *isa_bus;
isa_bus = isa_bus_new(DEVICE(d), pci_address_space(dev),
@@ -308,6 +309,16 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp)
if (!qdev_realize(DEVICE(&d->rtc), BUS(isa_bus), errp)) {
return;
}
+
+ /* USB */
+ if (d->has_usb) {
+ object_initialize_child(OBJECT(dev), "uhci", &d->uhci,
+ TYPE_PIIX3_USB_UHCI);
+ qdev_prop_set_int32(DEVICE(&d->uhci), "addr", dev->devfn + 2);
+ if (!qdev_realize(DEVICE(&d->uhci), BUS(pci_bus), errp)) {
+ return;
+ }
+ }
}
static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope)
@@ -341,6 +352,11 @@ static void pci_piix3_init(Object *obj)
object_initialize_child(obj, "rtc", &d->rtc, TYPE_MC146818_RTC);
}
+static Property pci_piix3_props[] = {
+ DEFINE_PROP_BOOL("has-usb", PIIX3State, has_usb, true),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
static void pci_piix3_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -360,6 +376,7 @@ static void pci_piix3_class_init(ObjectClass *klass, void
*data)
* pc_piix.c's pc_init1()
*/
dc->user_creatable = false;
+ device_class_set_props(dc, pci_piix3_props);
adevc->build_dev_aml = build_pci_isa_aml;
}
diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig
index c10cbc5fc1..f01bc0dff3 100644
--- a/hw/isa/Kconfig
+++ b/hw/isa/Kconfig
@@ -36,6 +36,7 @@ config PIIX3
select I8257
select ISA_BUS
select MC146818RTC
+ select USB_UHCI
config PIIX4
bool
--
2.39.0
- [PATCH v6 06/33] hw/isa/piix4: Decouple INTx-to-LNKx routing which is board-specific, (continued)
- [PATCH v6 06/33] hw/isa/piix4: Decouple INTx-to-LNKx routing which is board-specific, Bernhard Beschow, 2023/01/09
- [PATCH v6 07/33] hw/mips/Kconfig: Track Malta's PIIX dependencies via Kconfig, Bernhard Beschow, 2023/01/09
- [PATCH v6 08/33] hw/usb/hcd-uhci: Introduce TYPE_ defines for device models, Bernhard Beschow, 2023/01/09
- [PATCH v6 10/33] hw/intc/i8259: Introduce i8259 proxy TYPE_ISA_PIC, Bernhard Beschow, 2023/01/09
- [PATCH v6 09/33] hw/intc/i8259: Make using the isa_pic singleton more type-safe, Bernhard Beschow, 2023/01/09
- [PATCH v6 11/33] hw/i386/pc: Create RTC controllers in south bridges, Bernhard Beschow, 2023/01/09
- [PATCH v6 12/33] hw/i386/pc: No need for rtc_state to be an out-parameter, Bernhard Beschow, 2023/01/09
- [PATCH v6 17/33] hw/isa/piix3: Create IDE controller in host device, Bernhard Beschow, 2023/01/09
- [PATCH v6 14/33] hw/isa/piix3: Create USB controller in host device,
Bernhard Beschow <=
- [PATCH v6 16/33] hw/isa/piix3: Create TYPE_ISA_PIC in host device, Bernhard Beschow, 2023/01/09
- [PATCH v6 18/33] hw/isa/piix3: Wire up ACPI interrupt internally, Bernhard Beschow, 2023/01/09
- [PATCH v6 13/33] hw/i386/pc_piix: Allow for setting properties before realizing PIIX3 south bridge, Bernhard Beschow, 2023/01/09
- [PATCH v6 21/33] hw/isa/piix3: Rename piix3_reset() for sharing with PIIX4, Bernhard Beschow, 2023/01/09
- [PATCH v6 20/33] hw/isa/piix3: Rename pci_piix3_props for sharing with PIIX4, Bernhard Beschow, 2023/01/09
- [PATCH v6 15/33] hw/isa/piix3: Create power management controller in host device, Bernhard Beschow, 2023/01/09
- [PATCH v6 23/33] hw/isa/piix4: Make PIIX4's ACPI and USB functions optional, Bernhard Beschow, 2023/01/09