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[PULL 06/10] target/ppc: Use SMT4 small core chip type in POWER9/10 PVRs
From: |
Daniel Henrique Barboza |
Subject: |
[PULL 06/10] target/ppc: Use SMT4 small core chip type in POWER9/10 PVRs |
Date: |
Sun, 28 May 2023 13:49:18 -0300 |
From: Nicholas Piggin <npiggin@gmail.com>
QEMU's PVR value for POWER9 DD2.0 has chip type 1, which is the SMT4
"small core" type that OpenPOWER processors use. QEMU's PVR for all
other POWER9/10 have chip type 0, which "enterprise" systems use.
The difference does not really matter to QEMU (because it does not care
about SMT mode in the target), but for consistency all PVRs should use
the same chip type. We'll go with the SMT4 OpenPOWER type.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20230515160131.394562-1-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
target/ppc/cpu-models.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h
index 1326493a9a..a77e036b3a 100644
--- a/target/ppc/cpu-models.h
+++ b/target/ppc/cpu-models.h
@@ -348,11 +348,11 @@ enum {
CPU_POWERPC_POWER8NVL_BASE = 0x004C0000,
CPU_POWERPC_POWER8NVL_v10 = 0x004C0100,
CPU_POWERPC_POWER9_BASE = 0x004E0000,
- CPU_POWERPC_POWER9_DD1 = 0x004E0100,
+ CPU_POWERPC_POWER9_DD1 = 0x004E1100,
CPU_POWERPC_POWER9_DD20 = 0x004E1200,
CPU_POWERPC_POWER10_BASE = 0x00800000,
- CPU_POWERPC_POWER10_DD1 = 0x00800100,
- CPU_POWERPC_POWER10_DD20 = 0x00800200,
+ CPU_POWERPC_POWER10_DD1 = 0x00801100,
+ CPU_POWERPC_POWER10_DD20 = 0x00801200,
CPU_POWERPC_970_v22 = 0x00390202,
CPU_POWERPC_970FX_v10 = 0x00391100,
CPU_POWERPC_970FX_v20 = 0x003C0200,
--
2.40.1
- [PULL 00/10] ppc queue, Daniel Henrique Barboza, 2023/05/28
- [PULL 01/10] target/ppc: Fix fallback to MFSS for MFFS* instructions on pre 3.0 ISAs, Daniel Henrique Barboza, 2023/05/28
- [PULL 02/10] target/ppc: Fix width of some 32-bit SPRs, Daniel Henrique Barboza, 2023/05/28
- [PULL 03/10] target/ppc: Alignment faults do not set DSISR in ISA v3.0 onward, Daniel Henrique Barboza, 2023/05/28
- [PULL 04/10] spapr: Add SPAPR_CAP_AIL_MODE_3 for AIL mode 3 support for H_SET_MODE hcall, Daniel Henrique Barboza, 2023/05/28
- [PULL 05/10] hw/ppc/prep: Fix wiring of PIC -> CPU interrupt, Daniel Henrique Barboza, 2023/05/28
- [PULL 07/10] pnv_lpc: disable reentrancy detection for lpc-hc, Daniel Henrique Barboza, 2023/05/28
- [PULL 06/10] target/ppc: Use SMT4 small core chip type in POWER9/10 PVRs,
Daniel Henrique Barboza <=
- [PULL 08/10] target/ppc: Merge COMPUTE_CLASS and COMPUTE_FPRF, Daniel Henrique Barboza, 2023/05/28
- [PULL 09/10] target/ppc: Add POWER9 DD2.2 model, Daniel Henrique Barboza, 2023/05/28
- [PULL 10/10] ppc/pegasos2: Change default CPU to 7457, Daniel Henrique Barboza, 2023/05/28
- Re: [PULL 00/10] ppc queue, Michael Tokarev, 2023/05/28
- Re: [PULL 00/10] ppc queue, Daniel Henrique Barboza, 2023/05/29