Re: [PATCH 3/4] pnv/xive2: Allow writes to the Physical Thread Enable registers

[Cédric Le Goater]

On 5/30/23 18:11, Frederic Barrat wrote:
> Fix what was probably a silly mistake and allow to write the Physical
> Thread enable registers 0 and 1. Skiboot prefers to use the ENx_SET
> variant so it went unnoticed, but there's no reason to discard a write
> to the full register, it is Read-Write.

Indeed.


> Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>

Fixes: da71b7e3ed45 ("ppc/pnv: Add a XIVE2 controller to the POWER10 chip")

Reviewed-by: Cédric Le Goater <clg@kaod.org>

Thanks,

C.



> ---
>   hw/intc/pnv_xive2.c | 1 +
>   1 file changed, 1 insertion(+)
>
> diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c
> index a75ff270ac..132f82a035 100644
> --- a/hw/intc/pnv_xive2.c
> +++ b/hw/intc/pnv_xive2.c
> @@ -1294,6 +1294,7 @@ static void pnv_xive2_ic_tctxt_write(void *opaque, hwaddr 
> offset,
>        */
>       case TCTXT_EN0: /* Physical Thread Enable */
>       case TCTXT_EN1: /* Physical Thread Enable (fused core) */
> +        xive->tctxt_regs[reg] = val;
>           break;
>   
>       case TCTXT_EN0_SET: