[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 27/60] pnv/xive: Allow mmio operations of any size on the ESB CI p
From: |
Daniel Henrique Barboza |
Subject: |
[PULL 27/60] pnv/xive: Allow mmio operations of any size on the ESB CI pages |
Date: |
Fri, 7 Jul 2023 08:30:35 -0300 |
From: Frederic Barrat <fbarrat@linux.ibm.com>
We currently only allow 64-bit operations on the ESB CI pages. There's
no real reason for that limitation, skiboot/linux didn't need
more. However the hardware supports any size, so this patch relaxes
that restriction. It impacts both the ESB pages for "normal"
interrupts as well as the ESB pages for escalation interrupts defined
for the ENDs.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-ID: <20230704144848.164287-1-fbarrat@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
hw/intc/xive.c | 8 ++++----
hw/intc/xive2.c | 4 ++--
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index f60c878345..c014e961a4 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -1175,11 +1175,11 @@ static const MemoryRegionOps xive_source_esb_ops = {
.write = xive_source_esb_write,
.endianness = DEVICE_BIG_ENDIAN,
.valid = {
- .min_access_size = 8,
+ .min_access_size = 1,
.max_access_size = 8,
},
.impl = {
- .min_access_size = 8,
+ .min_access_size = 1,
.max_access_size = 8,
},
};
@@ -2006,11 +2006,11 @@ static const MemoryRegionOps xive_end_source_ops = {
.write = xive_end_source_write,
.endianness = DEVICE_BIG_ENDIAN,
.valid = {
- .min_access_size = 8,
+ .min_access_size = 1,
.max_access_size = 8,
},
.impl = {
- .min_access_size = 8,
+ .min_access_size = 1,
.max_access_size = 8,
},
};
diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c
index 4d9ff41956..c37ef25d44 100644
--- a/hw/intc/xive2.c
+++ b/hw/intc/xive2.c
@@ -954,11 +954,11 @@ static const MemoryRegionOps xive2_end_source_ops = {
.write = xive2_end_source_write,
.endianness = DEVICE_BIG_ENDIAN,
.valid = {
- .min_access_size = 8,
+ .min_access_size = 1,
.max_access_size = 8,
},
.impl = {
- .min_access_size = 8,
+ .min_access_size = 1,
.max_access_size = 8,
},
};
--
2.41.0
- [PULL 17/60] target/ppc: Get CPUState in one step, (continued)
- [PULL 17/60] target/ppc: Get CPUState in one step, Daniel Henrique Barboza, 2023/07/07
- [PULL 18/60] target: ppc: Use MSR_HVB bit to get the target endianness for memory dump, Daniel Henrique Barboza, 2023/07/07
- [PULL 19/60] pnv/xive2: Fix TIMA offset for indirect access, Daniel Henrique Barboza, 2023/07/07
- [PULL 20/60] pnv/xive: Add property on xive sources to define PQ state on reset, Daniel Henrique Barboza, 2023/07/07
- [PULL 21/60] pnv/psi: Initialize the PSIHB interrupts to match hardware, Daniel Henrique Barboza, 2023/07/07
- [PULL 22/60] ppc/pnv: quad xscom callbacks are P9 specific, Daniel Henrique Barboza, 2023/07/07
- [PULL 23/60] ppc/pnv: Subclass quad xscom callbacks, Daniel Henrique Barboza, 2023/07/07
- [PULL 24/60] ppc/pnv: Add P10 quad xscom model, Daniel Henrique Barboza, 2023/07/07
- [PULL 25/60] ppc/pnv: Add P10 core xscom model, Daniel Henrique Barboza, 2023/07/07
- [PULL 26/60] ppc/pnv: Return zero for core thread state xscom, Daniel Henrique Barboza, 2023/07/07
- [PULL 27/60] pnv/xive: Allow mmio operations of any size on the ESB CI pages,
Daniel Henrique Barboza <=
- [PULL 28/60] ppc/pegasos2: Add support for -initrd command line option, Daniel Henrique Barboza, 2023/07/07
- [PULL 29/60] pnv/xive: Print CPU target in all TIMA traces, Daniel Henrique Barboza, 2023/07/07
- [PULL 30/60] pnv/xive2: Always pass a presenter object when accessing the TIMA, Daniel Henrique Barboza, 2023/07/07
- [PULL 31/60] target/ppc: Add LPAR-per-core vs per-thread mode flag, Daniel Henrique Barboza, 2023/07/07
- [PULL 32/60] target/ppc: SMT support for the HID SPR, Daniel Henrique Barboza, 2023/07/07
- [PULL 33/60] ppc/pnv: SMT support for powernv, Daniel Henrique Barboza, 2023/07/07
- [PULL 34/60] tests/avocado: Add powernv machine test script, Daniel Henrique Barboza, 2023/07/07
- [PULL 35/60] ppc440: Change ppc460ex_pcie_init() parameter type, Daniel Henrique Barboza, 2023/07/07
- [PULL 36/60] ppc440: Add cpu link property to PCIe controller model, Daniel Henrique Barboza, 2023/07/07
- [PULL 37/60] ppc440: Add a macro to shorten PCIe controller DCR registration, Daniel Henrique Barboza, 2023/07/07