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[PATCH 05/26] target/ppc: Update gdbstub to read SPR's CFAR, DEC, HDEC,
From: |
Nicholas Piggin |
Subject: |
[PATCH 05/26] target/ppc: Update gdbstub to read SPR's CFAR, DEC, HDEC, TB-L/U |
Date: |
Fri, 19 Jan 2024 01:06:23 +1000 |
From: Saif Abrar <saif.abrar@linux.vnet.ibm.com>
SPR's CFAR, DEC, HDEC, TB-L/U are not implemented as part of CPUPPCState.
Hence, gdbstub is not able to access them using (CPUPPCState *)env->spr[] array.
Update gdb_get_spr_reg() method to handle these SPR's specifically.
Signed-off-by: Saif Abrar <saif.abrar@linux.vnet.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
target/ppc/gdbstub.c | 40 ++++++++++++++++++++++++++++++++++++++--
1 file changed, 38 insertions(+), 2 deletions(-)
diff --git a/target/ppc/gdbstub.c b/target/ppc/gdbstub.c
index ec5731e5d6..dfe31d0f47 100644
--- a/target/ppc/gdbstub.c
+++ b/target/ppc/gdbstub.c
@@ -394,7 +394,32 @@ static int gdb_get_spr_reg(CPUPPCState *env, GByteArray
*buf, int n)
}
len = TARGET_LONG_SIZE;
- gdb_get_regl(buf, env->spr[reg]);
+
+ /* Handle those SPRs that are not part of the env->spr[] array */
+ target_ulong val;
+ switch (reg) {
+#if defined(TARGET_PPC64)
+ case SPR_CFAR:
+ val = env->cfar;
+ break;
+#endif
+ case SPR_HDEC:
+ val = cpu_ppc_load_hdecr(env);
+ break;
+ case SPR_TBL:
+ val = cpu_ppc_load_tbl(env);
+ break;
+ case SPR_TBU:
+ val = cpu_ppc_load_tbu(env);
+ break;
+ case SPR_DECR:
+ val = cpu_ppc_load_decr(env);
+ break;
+ default:
+ val = env->spr[reg];
+ }
+ gdb_get_regl(buf, val);
+
ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, len), len);
return len;
}
@@ -411,7 +436,18 @@ static int gdb_set_spr_reg(CPUPPCState *env, uint8_t
*mem_buf, int n)
len = TARGET_LONG_SIZE;
ppc_maybe_bswap_register(env, mem_buf, len);
- env->spr[reg] = ldn_p(mem_buf, len);
+
+ /* Handle those SPRs that are not part of the env->spr[] array */
+ target_ulong val = ldn_p(mem_buf, len);
+ switch (reg) {
+#if defined(TARGET_PPC64)
+ case SPR_CFAR:
+ env->cfar = val;
+ break;
+#endif
+ default:
+ env->spr[reg] = val;
+ }
return len;
}
--
2.42.0
- [PATCH 00/26] target/ppc: TCG improvements and fixes, Nicholas Piggin, 2024/01/18
- [PATCH 01/26] target/ppc: Fix crash on machine check caused by ifetch, Nicholas Piggin, 2024/01/18
- [PATCH 02/26] target/ppc: Prevent supervisor from modifying MSR[ME], Nicholas Piggin, 2024/01/18
- [PATCH 03/26] spapr: set MSR[ME] and MSR[FP] on client entry, Nicholas Piggin, 2024/01/18
- [PATCH 04/26] target/ppc: Rename registers to match ISA, Nicholas Piggin, 2024/01/18
- [PATCH 05/26] target/ppc: Update gdbstub to read SPR's CFAR, DEC, HDEC, TB-L/U,
Nicholas Piggin <=
- [PATCH 06/26] target/ppc: Rename TBL to TB on 64-bit, Nicholas Piggin, 2024/01/18
- [PATCH 07/26] target/ppc: Improve timebase register defines naming, Nicholas Piggin, 2024/01/18
- [PATCH 08/26] target/ppc: Fix move-to timebase SPR access permissions, Nicholas Piggin, 2024/01/18
- [PATCH 09/26] pnv/chiptod: Add POWER9/10 chiptod model, Nicholas Piggin, 2024/01/18
- [PATCH 10/26] ppc/pnv: Wire ChipTOD model to powernv9 and powernv10 machines, Nicholas Piggin, 2024/01/18
- [PATCH 11/26] pnv/chiptod: Implement the ChipTOD to Core transfer, Nicholas Piggin, 2024/01/18
- [PATCH 12/26] target/ppc: Implement core timebase state machine and TFMR, Nicholas Piggin, 2024/01/18
- [PATCH 13/26] target/ppc: Add SMT support to time facilities, Nicholas Piggin, 2024/01/18
- [PATCH 14/26] target/ppc: Add new hflags to support BHRB, Nicholas Piggin, 2024/01/18
- [PATCH 15/26] target/ppc: Add recording of taken branches to BHRB, Nicholas Piggin, 2024/01/18