[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH 09/14] target/ppc: add helper to write per-LPAR SPRs
From: |
Nicholas Piggin |
Subject: |
[PATCH 09/14] target/ppc: add helper to write per-LPAR SPRs |
Date: |
Sat, 18 May 2024 19:31:51 +1000 |
An SPR can be either per-thread, per-core, or per-LPAR. Per-LPAR means
per-thread or per-core, depending on 1LPAR mode.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
target/ppc/spr_common.h | 2 ++
target/ppc/translate.c | 26 ++++++++++++++++++++++++++
2 files changed, 28 insertions(+)
diff --git a/target/ppc/spr_common.h b/target/ppc/spr_common.h
index 9e40b3b608..85f73b860b 100644
--- a/target/ppc/spr_common.h
+++ b/target/ppc/spr_common.h
@@ -83,6 +83,8 @@ void spr_read_generic(DisasContext *ctx, int gprn, int sprn);
void spr_write_generic(DisasContext *ctx, int sprn, int gprn);
void spr_write_generic32(DisasContext *ctx, int sprn, int gprn);
void spr_core_write_generic(DisasContext *ctx, int sprn, int gprn);
+void spr_core_write_generic32(DisasContext *ctx, int sprn, int gprn);
+void spr_core_lpar_write_generic(DisasContext *ctx, int sprn, int gprn);
void spr_write_MMCR0(DisasContext *ctx, int sprn, int gprn);
void spr_write_MMCR1(DisasContext *ctx, int sprn, int gprn);
void spr_write_MMCRA(DisasContext *ctx, int sprn, int gprn);
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index c4b4f7ea62..ccd90a5feb 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -537,6 +537,32 @@ void spr_core_write_generic(DisasContext *ctx, int sprn,
int gprn)
spr_store_dump_spr(sprn);
}
+void spr_core_write_generic32(DisasContext *ctx, int sprn, int gprn)
+{
+ TCGv t0 = tcg_temp_new();
+ if (!(ctx->flags & POWERPC_FLAG_SMT)) {
+ spr_write_generic32(ctx, sprn, gprn);
+ return;
+ }
+
+ if (!gen_serialize(ctx)) {
+ return;
+ }
+
+ tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]);
+ gen_helper_spr_core_write_generic(tcg_env, tcg_constant_i32(sprn), t0);
+ spr_store_dump_spr(sprn);
+}
+
+void spr_core_lpar_write_generic(DisasContext *ctx, int sprn, int gprn)
+{
+ if (ctx->flags & POWERPC_FLAG_SMT_1LPAR) {
+ spr_core_write_generic(ctx, sprn, gprn);
+ } else {
+ spr_write_generic(ctx, sprn, gprn);
+ }
+}
+
static void spr_write_CTRL_ST(DisasContext *ctx, int sprn, int gprn)
{
/* This does not implement >1 thread */
--
2.43.0
- Re: [PATCH 02/14] target/ppc: Remove redundant MEMOP_GET_SIZE macro, (continued)
- [PATCH 03/14] target/ppc: Make checkstop actually stop the system, Nicholas Piggin, 2024/05/18
- [PATCH 04/14] target/ppc: improve checkstop logging, Nicholas Piggin, 2024/05/18
- [PATCH 06/14] target/ppc: BookE DECAR SPR is 32-bit, Nicholas Piggin, 2024/05/18
- [PATCH 07/14] target/ppc: Wire up BookE ATB registers for e500 family, Nicholas Piggin, 2024/05/18
- [PATCH 05/14] target/ppc: Implement attn instruction on BookS 64-bit processors, Nicholas Piggin, 2024/05/18
- [PATCH 09/14] target/ppc: add helper to write per-LPAR SPRs,
Nicholas Piggin <=
- [PATCH 11/14] target/ppc: Add SMT support to PTCR SPR, Nicholas Piggin, 2024/05/18
- [PATCH 08/14] target/ppc: Add PPR32 SPR, Nicholas Piggin, 2024/05/18
- [PATCH 10/14] target/ppc: Add SMT support to simple SPRs, Nicholas Piggin, 2024/05/18
- [PATCH 12/14] target/ppc: Implement LDBAR, TTR SPRs, Nicholas Piggin, 2024/05/18
- [PATCH 13/14] target/ppc: Implement SPRC/SPRD SPRs, Nicholas Piggin, 2024/05/18
- [PATCH 14/14] target/ppc: add SMT support to msgsnd broadcast, Nicholas Piggin, 2024/05/18