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[RFC PATCH 08/16] target/riscv: Allow global WG config to set WG CPU cal
From: |
Jim Shu |
Subject: |
[RFC PATCH 08/16] target/riscv: Allow global WG config to set WG CPU callbacks |
Date: |
Wed, 12 Jun 2024 16:14:08 +0800 |
Some WG CPU functions depend on global WG config (like num-of-world), so
we let the global WG config device to set callbacks of a RISC-V HART.
Signed-off-by: Jim Shu <jim.shu@sifive.com>
---
target/riscv/cpu.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 2d3bfedbba..50a0fba127 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -431,6 +431,10 @@ struct CPUArchState {
uint64_t kvm_timer_state;
uint64_t kvm_timer_frequency;
#endif /* CONFIG_KVM */
+
+ /* machine specific WorldGuard callback */
+ void (*wg_reset)(CPURISCVState *env);
+ void (*wid_to_mem_attrs)(MemTxAttrs *attrs, uint32_t wid);
};
/*
--
2.17.1
- [RFC PATCH 00/16] Implements RISC-V WorldGuard extension v0.4, Jim Shu, 2024/06/12
- [RFC PATCH 02/16] accel/tcg: memory access from CPU will pass access_type to IOMMU, Jim Shu, 2024/06/12
- [RFC PATCH 07/16] target/riscv: Add defines for WorldGuard CSRs, Jim Shu, 2024/06/12
- [RFC PATCH 09/16] target/riscv: Implement WorldGuard CSRs, Jim Shu, 2024/06/12
- [RFC PATCH 10/16] target/riscv: Add WID to MemTxAttrs of CPU memory transactions, Jim Shu, 2024/06/12