Re: [PATCH 07/13] ppc/xive2: Allow 1-byte write of Target field in TIMA

[Cédric Le Goater]

On 8/1/24 22:30, Michael Kowal wrote:
> From: Glenn Miles <milesg@linux.vnet.ibm.com>
>
> When running PowerVM, the console is littered with XIVE traces regarding
> invalid writes to TIMA address 0x100b6 due to a lack of support for writes
> to the "TARGET" field which was added for XIVE GEN2.  To fix this, we add
> special op support for 1-byte writes to this field.
>
> Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com>
> Signed-off-by: Michael Kowal <kowal@linux.ibm.com>


Reviewed-by: Cédric Le Goater <clg@redhat.com>

Thanks,

C.


> ---
>   include/hw/ppc/xive2.h     |  2 ++
>   include/hw/ppc/xive_regs.h |  1 +
>   hw/intc/xive.c             |  2 ++
>   hw/intc/xive2.c            | 13 +++++++++++++
>   4 files changed, 18 insertions(+)
>
> diff --git a/include/hw/ppc/xive2.h b/include/hw/ppc/xive2.h
> index b7a7c33ddd..36bd0e747f 100644
> --- a/include/hw/ppc/xive2.h
> +++ b/include/hw/ppc/xive2.h
> @@ -121,5 +121,7 @@ uint64_t xive2_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX 
> *tctx,
>                                  hwaddr offset, unsigned size);
>   void xive2_tm_pull_os_ctx_ol(XivePresenter *xptr, XiveTCTX *tctx,
>                                hwaddr offset, uint64_t value, unsigned size);
> +void xive2_tm_set_hv_target(XivePresenter *xptr, XiveTCTX *tctx,
> +                            hwaddr offset, uint64_t value, unsigned size);
>   
>   #endif /* PPC_XIVE2_H */
> diff --git a/include/hw/ppc/xive_regs.h b/include/hw/ppc/xive_regs.h
> index 27a744d50d..f8f05deafd 100644
> --- a/include/hw/ppc/xive_regs.h
> +++ b/include/hw/ppc/xive_regs.h
> @@ -79,6 +79,7 @@
>   #define TM_INC                  0x5  /*  -   +   -   +  */
>   #define TM_LGS                  0x5  /*  +   +   +   +  */ /* Rename P10 */
>   #define TM_AGE                  0x6  /*  -   +   -   +  */
> +#define TM_T                    0x6  /*  -   +   -   +  */ /* Rename P10 */
>   #define TM_PIPR                 0x7  /*  -   +   -   +  */
>   #define TM_OGEN                 0xF  /*  -   +   -   -  */ /* P10 only */
>   
> diff --git a/hw/intc/xive.c b/hw/intc/xive.c
> index 8605dd618f..6229a6f870 100644
> --- a/hw/intc/xive.c
> +++ b/hw/intc/xive.c
> @@ -546,6 +546,8 @@ static const XiveTmOp xive2_tm_operations[] = {
>                                                        NULL },
>       { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, NULL,
>                                                        xive_tm_vt_poll },
> +    { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_T,     1, xive2_tm_set_hv_target,
> +                                                     NULL },
>   
>       /* MMIOs above 2K : special operations with side effects */
>       { XIVE_TM_OS_PAGE, TM_SPC_ACK_OS_REG,         2, NULL,
> diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c
> index 9d19273bc8..eed0cc9c3c 100644
> --- a/hw/intc/xive2.c
> +++ b/hw/intc/xive2.c
> @@ -600,6 +600,19 @@ void xive2_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX 
> *tctx,
>       }
>   }
>   
> +static void xive2_tctx_set_target(XiveTCTX *tctx, uint8_t ring, uint8_t target)
> +{
> +    uint8_t *regs = &tctx->regs[ring];
> +
> +    regs[TM_T] = target;
> +}
> +
> +void xive2_tm_set_hv_target(XivePresenter *xptr, XiveTCTX *tctx,
> +                            hwaddr offset, uint64_t value, unsigned size)
> +{
> +    xive2_tctx_set_target(tctx, TM_QW3_HV_PHYS, value & 0xff);
> +}
> +
>   /*
>    * XIVE Router (aka. Virtualization Controller or IVRE)
>    */