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[PATCH v2 04/14] pnv/xive2: Support for "OS LGS Push" TIMA operation
From: |
Michael Kowal |
Subject: |
[PATCH v2 04/14] pnv/xive2: Support for "OS LGS Push" TIMA operation |
Date: |
Mon, 9 Sep 2024 16:10:28 -0500 |
From: Glenn Miles <milesg@linux.vnet.ibm.com>
Adds support for single byte writes to offset 0x15 of the TIMA address
space. This offset holds the Logical Server Group Size (LGS) field.
The field is used to evenly distribute the interrupt load among the
members of a group, but is unused in the current implementation so we
just support the writing of the value for now.
Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com>
Signed-off-by: Michael Kowal <kowal@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
---
hw/intc/xive.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 8e62c7e75f..8605dd618f 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -341,6 +341,19 @@ static void xive_tm_set_os_cppr(XivePresenter *xptr,
XiveTCTX *tctx,
xive_tctx_set_cppr(tctx, TM_QW1_OS, value & 0xff);
}
+static void xive_tctx_set_lgs(XiveTCTX *tctx, uint8_t ring, uint8_t lgs)
+{
+ uint8_t *regs = &tctx->regs[ring];
+
+ regs[TM_LGS] = lgs;
+}
+
+static void xive_tm_set_os_lgs(XivePresenter *xptr, XiveTCTX *tctx,
+ hwaddr offset, uint64_t value, unsigned size)
+{
+ xive_tctx_set_lgs(tctx, TM_QW1_OS, value & 0xff);
+}
+
/*
* Adjust the IPB to allow a CPU to process event queues of other
* priorities during one physical interrupt cycle.
@@ -525,6 +538,8 @@ static const XiveTmOp xive2_tm_operations[] = {
NULL },
{ XIVE_TM_HV_PAGE, TM_QW1_OS + TM_WORD2, 4, xive2_tm_push_os_ctx,
NULL },
+ { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_LGS, 1, xive_tm_set_os_lgs,
+ NULL },
{ XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, xive_tm_set_hv_cppr,
NULL },
{ XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, xive_tm_vt_push,
--
2.43.0
- [PATCH v2 00/14] XIVE2 changes for TIMA operations, Michael Kowal, 2024/09/09
- [PATCH v2 03/14] ppc/xive2: Support TIMA "Pull OS Context to Odd Thread Reporting Line", Michael Kowal, 2024/09/09
- [PATCH v2 04/14] pnv/xive2: Support for "OS LGS Push" TIMA operation,
Michael Kowal <=
- [PATCH v2 06/14] ppc/xive2: Dump the VP-group and crowd tables with 'info pic', Michael Kowal, 2024/09/09
- [PATCH v2 01/14] pnv/xive: TIMA patch sets pre-req alignment and formatting changes, Michael Kowal, 2024/09/09
- [PATCH v2 05/14] ppc/xive2: Dump more NVP state with 'info pic', Michael Kowal, 2024/09/09
- [PATCH v2 02/14] pnv/xive2: Define OGEN field in the TIMA, Michael Kowal, 2024/09/09
- [PATCH v2 07/14] ppc/xive2: Allow 1-byte write of Target field in TIMA, Michael Kowal, 2024/09/09
- [PATCH v2 08/14] ppc/xive2: Support "Pull Thread Context to Register" operation, Michael Kowal, 2024/09/09
- [PATCH v2 10/14] ppc/xive2: Support "Pull Thread Context to Odd Thread Reporting Line", Michael Kowal, 2024/09/09