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[PATCH v3 01/17] hw/microblaze: Restrict MemoryRegionOps are implemented
From: |
Philippe Mathieu-Daudé |
Subject: |
[PATCH v3 01/17] hw/microblaze: Restrict MemoryRegionOps are implemented as 32-bit |
Date: |
Fri, 8 Nov 2024 15:43:01 +0000 |
All these MemoryRegionOps read() and write() handlers are
implemented expecting 32-bit accesses. Clarify that setting
.impl.min/max_access_size fields.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20241105130431.22564-8-philmd@linaro.org>
---
hw/char/xilinx_uartlite.c | 4 ++++
hw/intc/xilinx_intc.c | 4 ++++
hw/net/xilinx_ethlite.c | 4 ++++
hw/timer/xilinx_timer.c | 4 ++++
4 files changed, 16 insertions(+)
diff --git a/hw/char/xilinx_uartlite.c b/hw/char/xilinx_uartlite.c
index f325084f8b..3022b3d8ef 100644
--- a/hw/char/xilinx_uartlite.c
+++ b/hw/char/xilinx_uartlite.c
@@ -170,6 +170,10 @@ static const MemoryRegionOps uart_ops = {
.read = uart_read,
.write = uart_write,
.endianness = DEVICE_NATIVE_ENDIAN,
+ .impl = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
.valid = {
.min_access_size = 1,
.max_access_size = 4
diff --git a/hw/intc/xilinx_intc.c b/hw/intc/xilinx_intc.c
index 6e5012e66e..8fb6b4f1a5 100644
--- a/hw/intc/xilinx_intc.c
+++ b/hw/intc/xilinx_intc.c
@@ -144,6 +144,10 @@ static const MemoryRegionOps pic_ops = {
.read = pic_read,
.write = pic_write,
.endianness = DEVICE_NATIVE_ENDIAN,
+ .impl = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
.valid = {
.min_access_size = 4,
.max_access_size = 4
diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c
index bd81290808..e84b4cdd35 100644
--- a/hw/net/xilinx_ethlite.c
+++ b/hw/net/xilinx_ethlite.c
@@ -170,6 +170,10 @@ static const MemoryRegionOps eth_ops = {
.read = eth_read,
.write = eth_write,
.endianness = DEVICE_NATIVE_ENDIAN,
+ .impl = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
.valid = {
.min_access_size = 4,
.max_access_size = 4
diff --git a/hw/timer/xilinx_timer.c b/hw/timer/xilinx_timer.c
index 32a9df69e0..383fc8b3c8 100644
--- a/hw/timer/xilinx_timer.c
+++ b/hw/timer/xilinx_timer.c
@@ -193,6 +193,10 @@ static const MemoryRegionOps timer_ops = {
.read = timer_read,
.write = timer_write,
.endianness = DEVICE_NATIVE_ENDIAN,
+ .impl = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
.valid = {
.min_access_size = 4,
.max_access_size = 4
--
2.45.2
- [PATCH v3 00/17] hw/microblaze: Allow running cross-endian vCPUs, Philippe Mathieu-Daudé, 2024/11/08
- [PATCH v3 01/17] hw/microblaze: Restrict MemoryRegionOps are implemented as 32-bit,
Philippe Mathieu-Daudé <=
- [PATCH v3 02/17] hw/microblaze: Propagate CPU endianness to microblaze_load_kernel(), Philippe Mathieu-Daudé, 2024/11/08
- [PATCH v3 03/17] hw/intc/xilinx_intc: Make device endianness configurable, Philippe Mathieu-Daudé, 2024/11/08
- [RFC PATCH v3 04/17] hw/net/xilinx_ethlite: Simplify by having configurable endianness, Philippe Mathieu-Daudé, 2024/11/08
- [PATCH v3 06/17] hw/timer/xilinx_timer: Make device endianness configurable, Philippe Mathieu-Daudé, 2024/11/08
- [RFC PATCH v3 05/17] hw/timer/xilinx_timer: Allow down to 8-bit memory access, Philippe Mathieu-Daudé, 2024/11/08
- [PATCH v3 08/17] hw/ssi/xilinx_spi: Make device endianness configurable, Philippe Mathieu-Daudé, 2024/11/08
- [PATCH v3 07/17] hw/char/xilinx_uartlite: Make device endianness configurable, Philippe Mathieu-Daudé, 2024/11/08
- [PATCH v3 09/17] hw/ssi/xilinx_spips: Make device endianness configurable, Philippe Mathieu-Daudé, 2024/11/08