Re: mac99 SMP

[Jd Lyons]

extern void __secondary_start_pmac_0(void);

extern int pmac_pfunc_base_install(void);

static void (*pmac_tb_freeze)(int freeze);

static u64 timebase;

static int tb_req;

/*

* Core 99 and later support

*/

static void smp_core99_give_timebase(void)

{

unsigned long flags;

local_irq_save(flags);

while(!tb_req)

barrier();

tb_req = 0;

(*pmac_tb_freeze)(1);

mb();

timebase = get_tb();

mb();

while (timebase)

barrier();

mb();

(*pmac_tb_freeze)(0);

mb();

local_irq_restore(flags);

}

static void __devinit smp_core99_take_timebase(void)

{

unsigned long flags;

local_irq_save(flags);

tb_req = 1;

mb();

while (!timebase)

barrier();

mb();

set_tb(timebase >> 32, timebase & 0xffffffff);

timebase = 0;

mb();

local_irq_restore(flags);

}

Some interesting stuff can be found in the old kernel sources too https://gitlab-external-production.whoi.edu/dgiaya/linux/-/blob/v2.6.12-rc5/arch/ppc64/kernel/pmac_smp.c?ref_type=tags Seems the PM3,1 is treated a little different than other G4 PowerMacs:

/* HW sync only on these platforms */
	if (!machine_is_compatible("PowerMac7,2") &&
	    !machine_is_compatible("PowerMac7,3") &&
	    !machine_is_compatible("RackMac3,1"))
		goto nohwsync;

On Mar 15, 2025, at 12:26 PM, BALATON Zoltan <balaton@eik.bme.hu> wrote:

If it works the same like soft-reset then not without also implementing the correspondig GPIO line to do what timebase-enable should do but I don't know what that does. Searching Linux source for timebase-enable finds one match in linux/arch/powerpc/platforms/powermac/smp.c where it sets core99_tb_gpio to the value read. Searching for that variable shows how it's used so you can try to guess from that what it should do. In QEMU this currently does nothing so you'd have to implement it if you think this causes the problem. The comment at the core99_tb_gpio variable declaration says Timebase freeze GPIO so I think it might need to freeze timebase counter of the CPU but I don't know if low or high is running or freeze and how to do that in QEMU. The levels can be found reading the rest of the code using this variable, how to hook it to a GPIO is shown in my reset GPIO patch and how to control timebase in QEMU is something I don't know so either try to find out from the code or try asking if you can describe the question so that somebody not following this discussion understand it.