Re: mac99 SMP

[Andrew Randrianasulu]

On Mon, Mar 31, 2025 at 7:31 PM Jd Lyons <lyons_dj@yahoo.com> wrote:

Snow Leopard DP PPC will kick 2 G4 CPUs but not any more.

If you add the ‘ soft-reset’ property to Openbios it will use that rather than kick the second CPU, and that fails because when don’t know how to implement ‘ soft-reset’ the way it’s expected to work on the real hardware.

For the G5 Quad SL DP PPC does work with all 4 CPUs, and I assume it uses ‘ soft-reset’ and maybe some other logic when it detects the Model or just 4 G5 CPUs.

We’ll have some work to do if we want 970’s to boot OS X anyway.

I’m not able to boot Linux with the 970/fx with my patched version of Qemu, so I broke something with only 1 CPU G5 and Linux booting.

You tried my slightly more minimal patch? I assume because it all TCG anyway host does not matter much?

Another idea is to use  another openbios build ...

 

I’m sure we could build our own mach_kernel for SL DP PPC to kick or ‘ soft-reset’ more than 2 CPUs, but that’s a project for another time, I only really care about Tiger until we get OS 9 working, because Tirger has Classic Mode and I still use OS 9 apps in my workflow from time to time.

Other than benchmarking and hacks I really only use OS 9 in Classic Mode anyway.

There was interesting comment in there specifically about 9 under X:

==== quote ====

 // According to our GPIO expert, when modifying this GPIO to enable the time base,
    // you write a 1 to the DATA DIRECTION bit (bit 2) to make the GPIO be an output,
    // and leave the DATA VALUE bit 0.
    // To disable the time base, you make the DATA DIRECTION bit 0 to make it an open collector,
    // leaving the DATA VALUE bit 0.  The data bit value will then float to a 1 value.
    //
    // However, this is not how Mac OS 9 does it, nor does the operation described
    // work in practice. What IS done on Mac OS 9, and what appears to work in practice is
    // to set the DATA DIRECTION and the DATA VALUE bits to 0 to enable the time base.
    // To disable, set the DATA DIRECTION bit to 1 (output) and the DATA VALUE bit remains 0.
    //
    // This sounds a lot like TIMEBASE_EN is not an active low signal to me ...

#if 0
// What Mac OS 9 does, as performed in a Mac OS X context.
// Mac OS 9 actually does the I/Os to the GPIOs directly without having to call KeyLargo to do it.
    if ( enable )
    {
        keyLargo->callPlatformFunction(keyLargo_safeReadRegUInt8, false, (void *)&gpioOffset, (void *)&value,
                                        (void *)0, (void *)0);
        // set DATA DIRECTION bit to 0 (open collector) and set the DATA VALUE bit to 0 as well
        // (actually, in Mac OS 9, the disabling and enabling all happens in the same routine, SynchClock(),
        // so in the enabling, I believe their assumption is that the DATA VALUE bit is already 0.
        // I include the DATA VALUE zeroing in the below code just to be explicit about what's expected.
        value = ( 0 << kMacRISC_GPIO_DIRECTION_BIT ); // DATA_VALUE bit (0) is also zero implicitly
        keyLargo->callPlatformFunction(keyLargo_writeRegUInt8, false, (void *)&gpioOffset, (void *)value,
                                        (void *)0, (void *)0);
        // eieio();             // done in writeRegUInt8()
    }
    else        // disable
    {
        // this seems like overkill, but perhaps this is done this way due to the way KeyLargo works
        // (or for a given machine, it must be done this way and the other machines don't mind/care?).
        keyLargo->callPlatformFunction(keyLargo_safeReadRegUInt8, false,
                                        (void *)&gpioOffset, (void *)&value, (void *)0, (void *)0);
        value &= ~ 0x01; // set DATA VALUE bit to 0
        keyLargo->callPlatformFunction(keyLargo_writeRegUInt8, false, (void *)&gpioOffset, (void *)value,
                                        (void *)0, (void *)0);
        // eieio();             // done in writeRegUInt8()
        value |= ( 1 << kMacRISC_GPIO_DIRECTION_BIT ); // set DATA DIRECTION bit to 1 (output)
        keyLargo->callPlatformFunction(keyLargo_writeRegUInt8, false, (void *)&gpioOffset, (void *)value,
                                        (void *)0, (void *)0);
       // eieio();              // done in writeRegUInt8()
        sync();
    }
#endif

== end of quote ===

 

So to me Tiger is really the system I get he most use out of.

On Mar 31, 2025, at 11:46 AM, Andrew Randrianasulu <randrianasulu@gmail.com> wrote:

пн, 31 мар. 2025 г., 18:15 Jd Lyons <lyons_dj@yahoo.com>:

I’ve noted that QT MPEG2 Encoder from DVD Studio Pro 1.5 only uses 2 CPUs.

If you just want to test, I’d use Cinebench 2000 it can use more than 2 cores under OS 9.

Thanks, rn my machine just busy updating 10.5 to 10.5.8

In meantime I found those definitions in Apple's sources:

https://github.com/apple-oss-distributions/AppleKeyLargo/blob/AppleKeyLargo-172.3.1/KeyLargo.h

kKeyLargoMPICGlobal0 = 0x1020, // MPIC global0 register

kKeyLargoMPICIPI0 = 0x10A0, // MPIC IPI0 vector/priority register

kKeyLargoMPICIPI1 = 0x10B0, // MPIC IPI1 vector/priority register

kKeyLargoMPICIPI2 = 0x10C0, // MPIC IPI2 vector/priority register

kKeyLargoMPICIPI3 = 0x10D0, // MPIC IPI3 vector/priority register

kKeyLargoMPICSpuriousVector = 0x10E0, // MPIC spurious vector register

kKeyLargoMPICTimeFreq = 0x10F0, // MPIC timer frequency reporting register

kKeyLargoMPICTimerBase0 = 0x1110, // MPIC timer 0 base count register

kKeyLargoMPICTimerBase1 = 0x1150, // MPIC timer 1 base count register

kKeyLargoMPICTimerBase2 = 0x1190, // MPIC timer 2 base count register

kKeyLargoMPICTimerBase3 = 0x11D0, // MPIC timer 3 base count register

kKeyLargoMPICIntSrcSize = 0x20,

kKeyLargoMPICIntSrcVectPriBase = 0x10000, // MPIC interrupt source vector/priority base offset

kKeyLargoMPICIntSrcDestBase = 0x10010, // MPIC interrupt source destination register base offset

kKeyLargoMPICP0CurrTaskPriority = 0x20080, // MPIC CPU 0 current task priority register

kKeyLargoMPICP1CurrTaskPriority = 0x21080, // MPIC CPU 1 current task priority register

kKeyLargoMPICP2CurrTaskPriority = 0x22080, // MPIC CPU 2 current task priority register

kKeyLargoMPICP3CurrTaskPriority = 0x23080 // MPIC CPU 3 current task priority register

};

so it looks like support for 4 cpu was there at least in 10.5.8 time but may be something broke in xnu/bootloader ? Or it was not supposed to work (no production 4*G4 machines as far as we know) so may be it was disabled lately, after 10.4.11 ?

<logo.png>

CineBench 2000

macintoshrepository.org

On Mar 31, 2025, at 9:16 AM, Andrew Randrianasulu <randrianasulu@gmail.com> wrote:

On Mon, Mar 31, 2025 at 4:10 PM Jd Lyons <lyons_dj@yahoo.com> wrote:

Did OS 9 still have the freeze issue?

Guess my applications does not trigger it? I can hang FCP by loading
too new mp4 from my Nokia e52, but otherwise it work?

Guess I need to bite this dvd studio download and see how it works :)

On Mar 31, 2025, at 8:50 AM, Andrew Randrianasulu <randrianasulu@gmail.com> wrote:

Anyway, I tried 9.2.2 and not sure if Final Cut Pro 2.x (yeah, prehistoric) was able to do any smp with 4 cpu, yet it was going slightly above 100% (host) on -smp 2.