Re: mac99 SMP

[Jd Lyons]

Hmmm…..

OS 9 seems to write 0x4 then 0x0 to disable the timebase for CPU1, while OS X 
seems to write 0x4 then 0x5.

So maybe I should override 0x0 and write 0x5 for OS 9?



> On Apr 21, 2025, at 5:45 PM, BALATON Zoltan <balaton@eik.bme.hu> wrote:
> 
> On Mon, 21 Apr 2025, Jd Lyons wrote:
>> It seems to be an issue with the ppc.c not being smp aware. When OS 9 stops 
>> the timebase for CPU1 it also stops the timebase for CPU0 as well.
> 
> That's how it should work. The timebase-enable controls timebase for all CPUs 
> and they should be connected together. AFAIU time sync works by stopping 
> timebase on all CPUs then copying the value from CPU0 to CPU1 then restarting 
> it. The TB counter is stopped so CPU0 too so it won't advance until CPU1 has 
> the same value. So there's probably nothing to resolve here.
> 
>> I guess linux and OS X have there own logic to sync the. Timebase for smp 
>> that is compatible with qemu, but OS 9 seems to be an edge case….
> 
> These may have a sofware fallback that can sync even without stopping but I 
> don't think Linux uses that as it tries to use the GPIO way on G4 mac99. 
> Maybe it just does not care if it does not work and the kernel does not need 
> it but apps would be confused if they are run on different CPUs and get 
> different values. Maybe you just did not find a test for that yet.
> 
> Regards,
> BALATON Zoltan