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[Qemu-riscv] [PATCH v5 35/35] target/riscv: Remaining rvc insn reuse 32
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From: |
Bastian Koppelmann |
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Subject: |
[Qemu-riscv] [PATCH v5 35/35] target/riscv: Remaining rvc insn reuse 32 bit translators |
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Date: |
Tue, 22 Jan 2019 10:29:09 +0100 |
only one translate functions of rvc needs to handle special cases. For
the other rvc insns we can remove the extra layer of indirection.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
---
target/riscv/insn16.decode | 37 +++++++++----------
target/riscv/insn_trans/trans_rvc.inc.c | 48 -------------------------
2 files changed, 17 insertions(+), 68 deletions(-)
diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
index 98dd672c7f..d88a0c78ab 100644
--- a/target/riscv/insn16.decode
+++ b/target/riscv/insn16.decode
@@ -46,19 +46,15 @@
&i imm rs1 rd !extern
&s imm rs1 rs2 !extern
&j imm rd !extern
+&b imm rs2 rs1 !extern
# Argument sets:
&ci imm rd
&ciw nzuimm rd
&cs_dw uimm rs1 rs2
-&cb imm rs1
&cr rd rs2
-&c_j imm
&c_shift shamt rd
-&c_ld uimm rd
-&c_sd uimm rs2
-
&c_addi16sp_lui imm_lui imm_addi16sp rd
# Formats 16:
@@ -70,20 +66,21 @@
@cs_2 ... ... ... .. ... .. &r rd=%rs1_3 rs1=%rs1_3 rs2=%rs2_3
@cs_d ... ... ... .. ... .. &s imm=%uimm_cl_d rs1=%rs1_3 rs2=%rs2_3
@cs_w ... ... ... .. ... .. &s imm=%uimm_cl_w rs1=%rs1_3 rs2=%rs2_3
address@hidden ... ... ... .. ... .. &cb imm=%imm_cb rs1=%rs1_3
address@hidden ... ........... .. &c_j imm=%imm_cj
address@hidden ... ... ... .. ... .. &b imm=%imm_cb rs1=%rs1_3 rs2=0
address@hidden ... ........... .. &j imm=%imm_cj rd=0
address@hidden ... . ..... ..... .. &c_ld uimm=%uimm_6bit_ld %rd
address@hidden ... . ..... ..... .. &c_ld uimm=%uimm_6bit_lw %rd
address@hidden ... . ..... ..... .. &c_sd uimm=%uimm_6bit_sd
rs2=%rs2_5
address@hidden ... . ..... ..... .. &c_sd uimm=%uimm_6bit_sw
rs2=%rs2_5
address@hidden ... . ..... ..... .. &i imm=%uimm_6bit_ld %rd rs1=2
address@hidden ... . ..... ..... .. &i imm=%uimm_6bit_lw %rd rs1=2
address@hidden ... . ..... ..... .. &s imm=%uimm_6bit_sd rs1=2
rs2=%rs2_5
address@hidden ... . ..... ..... .. &s imm=%uimm_6bit_sw rs1=2
rs2=%rs2_5
@c_addi16sp_lui ... . ..... ..... .. &c_addi16sp_lui %imm_lui %imm_addi16sp
%rd
@c_shift ... . .. ... ..... .. &c_shift rd=%rs1_3 shamt=%nzuimm_6bit
@c_shift2 ... . .. ... ..... .. &c_shift rd=%rd shamt=%nzuimm_6bit
address@hidden ... . .. ... ..... .. &ci imm=%imm_ci rd=%rs1_3
address@hidden ... . .. ... ..... .. &i imm=%imm_ci rd=%rs1_3 rs1=%rs1_3
+
# *** RV64C Standard Extension (Quadrant 0) ***
c_addi4spn 000 ........ ... 00 @ciw
@@ -98,20 +95,20 @@ c_li 010 . ..... ..... 01 @ci
c_addi16sp_lui 011 . ..... ..... 01 @c_addi16sp_lui # shares opc with
C.LUI
c_srli 100 . 00 ... ..... 01 @c_shift
c_srai 100 . 01 ... ..... 01 @c_shift
-c_andi 100 . 10 ... ..... 01 @c_andi
+andi 100 . 10 ... ..... 01 @c_andi
sub 100 0 11 ... 00 ... 01 @cs_2
xor 100 0 11 ... 01 ... 01 @cs_2
or 100 0 11 ... 10 ... 01 @cs_2
and 100 0 11 ... 11 ... 01 @cs_2
-c_j 101 ........... 01 @cj
-c_beqz 110 ... ... ..... 01 @cb
-c_bnez 111 ... ... ..... 01 @cb
+jal 101 ........... 01 @cj # c_j
+beq 110 ... ... ..... 01 @cb # c_beqz
+bne 111 ... ... ..... 01 @cb # c_bnez
# *** RV64C Standard Extension (Quadrant 2) ***
c_slli 000 . ..... ..... 10 @c_shift2
-c_fldsp 001 . ..... ..... 10 @c_ld
-c_lwsp 010 . ..... ..... 10 @c_lw
+fld 001 . ..... ..... 10 @c_ld # fldsp
+lw 010 . ..... ..... 10 @c_lw # lwsp
c_jr_mv 100 0 ..... ..... 10 @cr
c_ebreak_jalr_add 100 1 ..... ..... 10 @cr
-c_fsdsp 101 ...... ..... 10 @c_sd
-c_swsp 110 . ..... ..... 10 @c_sw
+fsd 101 ...... ..... 10 @c_sd # fsdsp
+sw 110 . ..... ..... 10 @c_sw # swsp
diff --git a/target/riscv/insn_trans/trans_rvc.inc.c
b/target/riscv/insn_trans/trans_rvc.inc.c
index db9119ec9b..631e72c8b5 100644
--- a/target/riscv/insn_trans/trans_rvc.inc.c
+++ b/target/riscv/insn_trans/trans_rvc.inc.c
@@ -98,30 +98,6 @@ static bool trans_c_srai(DisasContext *ctx, arg_c_srai *a)
return trans_srai(ctx, &arg);
}
-static bool trans_c_andi(DisasContext *ctx, arg_c_andi *a)
-{
- arg_andi arg = { .rd = a->rd, .rs1 = a->rd, .imm = a->imm };
- return trans_andi(ctx, &arg);
-}
-
-static bool trans_c_j(DisasContext *ctx, arg_c_j *a)
-{
- arg_jal arg = { .rd = 0, .imm = a->imm };
- return trans_jal(ctx, &arg);
-}
-
-static bool trans_c_beqz(DisasContext *ctx, arg_c_beqz *a)
-{
- arg_beq arg = { .rs1 = a->rs1, .rs2 = 0, .imm = a->imm };
- return trans_beq(ctx, &arg);
-}
-
-static bool trans_c_bnez(DisasContext *ctx, arg_c_bnez *a)
-{
- arg_bne arg = { .rs1 = a->rs1, .rs2 = 0, .imm = a->imm };
- return trans_bne(ctx, &arg);
-}
-
static bool trans_c_slli(DisasContext *ctx, arg_c_slli *a)
{
int shamt = a->shamt;
@@ -138,18 +114,6 @@ static bool trans_c_slli(DisasContext *ctx, arg_c_slli *a)
return trans_slli(ctx, &arg);
}
-static bool trans_c_fldsp(DisasContext *ctx, arg_c_fldsp *a)
-{
- arg_fld arg = { .rd = a->rd, .rs1 = 2, .imm = a->uimm };
- return trans_fld(ctx, &arg);
-}
-
-static bool trans_c_lwsp(DisasContext *ctx, arg_c_lwsp *a)
-{
- arg_lw arg = { .rd = a->rd, .rs1 = 2, .imm = a->uimm };
- return trans_lw(ctx, &arg);
-}
-
static bool trans_c_jr_mv(DisasContext *ctx, arg_c_jr_mv *a)
{
if (a->rd != 0 && a->rs2 == 0) {
@@ -183,15 +147,3 @@ static bool trans_c_ebreak_jalr_add(DisasContext *ctx,
arg_c_ebreak_jalr_add *a)
}
return false;
}
-
-static bool trans_c_fsdsp(DisasContext *ctx, arg_c_fsdsp *a)
-{
- arg_fsd arg = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm };
- return trans_fsd(ctx, &arg);
-}
-
-static bool trans_c_swsp(DisasContext *ctx, arg_c_swsp *a)
-{
- arg_sw arg = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm };
- return trans_sw(ctx, &arg);
-}
--
2.20.1
- [Qemu-riscv] [PATCH v5 00/35] target/riscv: Convert to decodetree, Bastian Koppelmann, 2019/01/22
- [Qemu-riscv] [PATCH v5 32/35] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns, Bastian Koppelmann, 2019/01/22
- [Qemu-riscv] [PATCH v5 28/35] target/riscv: Rename trans_arith to gen_arith, Bastian Koppelmann, 2019/01/22
- [Qemu-riscv] [PATCH v5 34/35] target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64, Bastian Koppelmann, 2019/01/22
- [Qemu-riscv] [PATCH v5 35/35] target/riscv: Remaining rvc insn reuse 32 bit translators,
Bastian Koppelmann <=
- [Qemu-riscv] [PATCH v5 30/35] target/riscv: Remove decode_RV32_64G(), Bastian Koppelmann, 2019/01/22
- [Qemu-riscv] [PATCH v5 33/35] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64, Bastian Koppelmann, 2019/01/22
- [Qemu-riscv] [PATCH v5 31/35] target/riscv: Convert @cs_2 insns to share translation functions, Bastian Koppelmann, 2019/01/22
- [Qemu-riscv] [PATCH v5 29/35] target/riscv: Remove gen_system(), Bastian Koppelmann, 2019/01/22
- [Qemu-riscv] [PATCH v5 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions, Bastian Koppelmann, 2019/01/22
- [Qemu-riscv] [PATCH v5 21/35] target/riscv: Remove manual decoding from gen_branch(), Bastian Koppelmann, 2019/01/22
- [Qemu-riscv] [PATCH v5 27/35] target/riscv: Remove manual decoding of RV32/64M insn, Bastian Koppelmann, 2019/01/22
- [Qemu-riscv] [PATCH v5 13/35] target/riscv: Convert RV64F insns to decodetree, Bastian Koppelmann, 2019/01/22