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qemu-riscv (date)
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Last Modified: Thu Feb 28 2019 10:04:33 -0500
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February 28, 2019
Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree
,
Paolo Bonzini
,
10:04
Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree
,
Thomas Huth
,
03:51
February 27, 2019
Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree
,
no-reply
,
16:48
Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree
,
no-reply
,
16:44
Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree
,
no-reply
,
16:39
Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree
,
no-reply
,
16:34
Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree
,
no-reply
,
16:28
Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree
,
no-reply
,
16:22
Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree
,
no-reply
,
16:11
Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree
,
no-reply
,
16:06
Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree
,
no-reply
,
16:02
Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree
,
no-reply
,
15:57
Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree
,
no-reply
,
15:53
Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree
,
no-reply
,
15:48
Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree
,
no-reply
,
15:44
Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree
,
no-reply
,
15:39
Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree
,
no-reply
,
15:34
Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree
,
no-reply
,
15:28
Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree
,
no-reply
,
15:24
Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree
,
no-reply
,
15:18
Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree
,
no-reply
,
15:18
Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree
,
no-reply
,
15:13
Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree
,
no-reply
,
14:53
Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree
,
no-reply
,
14:26
Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree
,
no-reply
,
14:20
Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree
,
no-reply
,
14:14
Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree
,
no-reply
,
14:09
Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree
,
no-reply
,
14:03
Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree
,
no-reply
,
13:58
Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree
,
no-reply
,
13:54
Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree
,
no-reply
,
13:41
Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree
,
no-reply
,
13:37
Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree
,
no-reply
,
13:31
Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree
,
no-reply
,
13:11
February 26, 2019
Re: [Qemu-riscv] [Qemu-devel] [PATCH] riscv: Add proper alignment check and pending 'C' extension upon misa writes
,
Amed Magdy
,
03:11
Re: [Qemu-riscv] [Qemu-devel] [PATCH] riscv: Add proper alignment check and pending 'C' extension upon misa writes
,
Amed Magdy
,
02:59
February 25, 2019
Re: [Qemu-riscv] [Qemu-devel] [PATCH] riscv: Add proper alignment check and pending 'C' extension upon misa writes
,
Eric Blake
,
09:15
February 24, 2019
Re: [Qemu-riscv] [Qemu-devel] [PATCH] riscv: Add proper alignment check and pending 'C' extension upon misa writes
,
Richard Henderson
,
14:04
Re: [Qemu-riscv] [Qemu-devel] [PATCH] riscv: Add proper alignment check and pending 'C' extension upon misa writes
,
Amed Magdy
,
03:07
Re: [Qemu-riscv] [Qemu-devel] [PATCH] riscv: Add proper alignment check and pending 'C' extension upon misa writes
,
Amed Magdy
,
02:58
February 23, 2019
Re: [Qemu-riscv] [Qemu-devel] [PATCH] riscv: Add proper alignment check and pending 'C' extension upon misa writes
,
Eric Blake
,
16:46
February 22, 2019
Re: [Qemu-riscv] [Qemu-devel] [PATCH] riscv: Add proper alignment check and pending 'C' extension upon misa writes
,
Richard Henderson
,
18:57
Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree
,
Alistair Francis
,
18:17
[Qemu-riscv] [PATCH] riscv: Add proper alignment check and pending 'C' extension upon misa writes
,
amagdy . afifi
,
17:35
[Qemu-riscv] Add proper alignment check and pending 'C' extension for riscv
,
amagdy . afifi
,
17:35
[Qemu-riscv] [PATCH v8 24/34] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
,
Bastian Koppelmann
,
09:14
[Qemu-riscv] [PATCH v8 32/34] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
,
Bastian Koppelmann
,
09:14
[Qemu-riscv] [PATCH v8 02/34] target/riscv: Convert RVXI branch insns to decodetree
,
Bastian Koppelmann
,
09:13
[Qemu-riscv] [PATCH v8 20/34] target/riscv: Remove manual decoding from gen_branch()
,
Bastian Koppelmann
,
09:13
[Qemu-riscv] [PATCH v8 17/34] target/riscv: Convert quadrant 1 of RVXC insns to decodetree
,
Bastian Koppelmann
,
09:13
[Qemu-riscv] [PATCH v8 23/34] target/riscv: Move gen_arith_imm() decoding into trans_* functions
,
Bastian Koppelmann
,
09:13
[Qemu-riscv] [PATCH v8 30/34] target/riscv: Convert @cs_2 insns to share translation functions
,
Bastian Koppelmann
,
09:13
[Qemu-riscv] [PATCH v8 34/34] target/riscv: Remaining rvc insn reuse 32 bit translators
,
Bastian Koppelmann
,
09:13
[Qemu-riscv] [PATCH v8 13/34] target/riscv: Convert RV32D insns to decodetree
,
Bastian Koppelmann
,
09:13
[Qemu-riscv] [PATCH v8 31/34] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
,
Bastian Koppelmann
,
09:13
[Qemu-riscv] [PATCH v8 05/34] target/riscv: Convert RVXI arithmetic insns to decodetree
,
Bastian Koppelmann
,
09:13
[Qemu-riscv] [PATCH v8 28/34] target/riscv: Remove gen_system()
,
Bastian Koppelmann
,
09:13
[Qemu-riscv] [PATCH v8 12/34] target/riscv: Convert RV64F insns to decodetree
,
Bastian Koppelmann
,
09:13
[Qemu-riscv] [PATCH v8 26/34] target/riscv: Remove manual decoding of RV32/64M insn
,
Bastian Koppelmann
,
09:13
[Qemu-riscv] [PATCH v8 06/34] target/riscv: Convert RVXI fence insns to decodetree
,
Bastian Koppelmann
,
09:13
[Qemu-riscv] [PATCH v8 33/34] target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
,
Bastian Koppelmann
,
09:13
[Qemu-riscv] [PATCH v8 22/34] target/riscv: Remove manual decoding from gen_store()
,
Bastian Koppelmann
,
09:13
[Qemu-riscv] [PATCH v8 19/34] target/riscv: Remove gen_jalr()
,
Bastian Koppelmann
,
09:13
[Qemu-riscv] [PATCH v8 29/34] target/riscv: Remove decode_RV32_64G()
,
Bastian Koppelmann
,
09:13
[Qemu-riscv] [PATCH v8 27/34] target/riscv: Rename trans_arith to gen_arith
,
Bastian Koppelmann
,
09:13
[Qemu-riscv] [PATCH v8 25/34] target/riscv: Remove shift and slt insn manual decoding
,
Bastian Koppelmann
,
09:13
[Qemu-riscv] [PATCH v8 21/34] target/riscv: Remove manual decoding from gen_load()
,
Bastian Koppelmann
,
09:12
[Qemu-riscv] [PATCH v8 18/34] target/riscv: Convert quadrant 2 of RVXC insns to decodetree
,
Bastian Koppelmann
,
09:12
[Qemu-riscv] [PATCH v8 10/34] target/riscv: Convert RV64A insns to decodetree
,
Bastian Koppelmann
,
09:12
[Qemu-riscv] [PATCH v8 09/34] target/riscv: Convert RV32A insns to decodetree
,
Bastian Koppelmann
,
09:12
[Qemu-riscv] [PATCH v8 11/34] target/riscv: Convert RV32F insns to decodetree
,
Bastian Koppelmann
,
09:12
[Qemu-riscv] [PATCH v8 04/34] target/riscv: Convert RV64I load/store insns to decodetree
,
Bastian Koppelmann
,
09:12
[Qemu-riscv] [PATCH v8 03/34] target/riscv: Convert RV32I load/store insns to decodetree
,
Bastian Koppelmann
,
09:12
[Qemu-riscv] [PATCH v8 07/34] target/riscv: Convert RVXI csr insns to decodetree
,
Bastian Koppelmann
,
09:12
[Qemu-riscv] [PATCH v8 00/34] target/riscv: Convert to decodetree
,
Bastian Koppelmann
,
09:12
[Qemu-riscv] [PATCH v8 01/34] target/riscv: Activate decodetree and implemnt LUI & AUIPC
,
Bastian Koppelmann
,
09:12
[Qemu-riscv] [PATCH v8 14/34] target/riscv: Convert RV64D insns to decodetree
,
Bastian Koppelmann
,
09:12
[Qemu-riscv] [PATCH v8 08/34] target/riscv: Convert RVXM insns to decodetree
,
Bastian Koppelmann
,
09:12
[Qemu-riscv] [PATCH v8 16/34] target/riscv: Convert quadrant 0 of RVXC insns to decodetree
,
Bastian Koppelmann
,
09:11
[Qemu-riscv] [PATCH v8 15/34] target/riscv: Convert RV priv insns to decodetree
,
Bastian Koppelmann
,
09:11
February 21, 2019
Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 00/35] target/riscv: Convert to decodetree
,
Palmer Dabbelt
,
12:24
February 20, 2019
[Qemu-riscv] [PATCH v2 08/11] RISC-V: Add support for vectored interrupts
,
Alistair Francis
,
19:45
[Qemu-riscv] [PATCH v2 09/11] RISC-V: Convert trap debugging to trace events
,
Alistair Francis
,
19:45
[Qemu-riscv] [PATCH v2 11/11] riscv: sifive_u: Allow up to 4 CPUs to be created
,
Alistair Francis
,
19:45
[Qemu-riscv] [PATCH v2 10/11] RISC-V: Update load reservation comment in do_interrupt
,
Alistair Francis
,
19:45
[Qemu-riscv] [PATCH v2 07/11] RISC-V: Change local interrupts from edge to level
,
Alistair Francis
,
19:44
[Qemu-riscv] [PATCH v2 06/11] RISC-V: linux-user support for RVE ABI
,
Alistair Francis
,
19:44
[Qemu-riscv] [PATCH v2 04/11] RISC-V: Remove unnecessary disassembler constraints
,
Alistair Francis
,
19:44
[Qemu-riscv] [PATCH v2 01/11] riscv: pmp: Log pmp access errors as guest errors
,
Alistair Francis
,
19:44
[Qemu-riscv] [PATCH v2 05/11] elf: Add RISC-V PSABI ELF header defines
,
Alistair Francis
,
19:44
[Qemu-riscv] [PATCH v2 03/11] RISC-V: Allow interrupt controllers to claim interrupts
,
Alistair Francis
,
19:44
[Qemu-riscv] [PATCH v2 02/11] RISC-V: Replace __builtin_popcount with ctpop8 in PLIC
,
Alistair Francis
,
19:44
[Qemu-riscv] [PATCH v2 00/11] Upstream RISC-V fork patches, part 4
,
Alistair Francis
,
19:44
Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 00/35] target/riscv: Convert to decodetree
,
Bastian Koppelmann
,
12:03
February 15, 2019
Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 00/35] target/riscv: Convert to decodetree
,
no-reply
,
12:11
Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 00/35] target/riscv: Convert to decodetree
,
no-reply
,
11:43
Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 00/35] target/riscv: Convert to decodetree
,
no-reply
,
11:39
Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 00/35] target/riscv: Convert to decodetree
,
no-reply
,
11:01
Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 00/35] target/riscv: Convert to decodetree
,
no-reply
,
10:14
Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 00/35] target/riscv: Convert to decodetree
,
no-reply
,
09:43
Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 00/35] target/riscv: Convert to decodetree
,
no-reply
,
09:24
Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 00/35] target/riscv: Convert to decodetree
,
no-reply
,
09:12
Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 00/35] target/riscv: Convert to decodetree
,
no-reply
,
08:42
Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 00/35] target/riscv: Convert to decodetree
,
Bastian Koppelmann
,
08:13
Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 00/35] target/riscv: Convert to decodetree
,
no-reply
,
08:11
Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 00/35] target/riscv: Convert to decodetree
,
no-reply
,
08:08
Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 00/35] target/riscv: Convert to decodetree
,
no-reply
,
07:41
Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 00/35] target/riscv: Convert to decodetree
,
no-reply
,
07:37
Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 21/35] target/riscv: Remove manual decoding from gen_branch()
,
Bastian Koppelmann
,
07:15
Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 20/35] target/riscv: Remove gen_jalr()
,
Bastian Koppelmann
,
07:15
Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 16/35] target/riscv: Convert RV priv insns to decodetree
,
Bastian Koppelmann
,
07:13
Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 12/35] target/riscv: Convert RV32F insns to decodetree
,
Bastian Koppelmann
,
07:11
Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 10/35] target/riscv: Convert RV32A insns to decodetree
,
Bastian Koppelmann
,
07:10
February 14, 2019
Re: [Qemu-riscv] [PULL] RISC-V Patches for the 4.0 Soft Freeze, Part 1
,
Peter Maydell
,
09:34
February 13, 2019
Re: [Qemu-riscv] [Qemu-devel] [PATCH v6 00/35] target/riscv: Convert to decodetree
,
Palmer Dabbelt
,
19:51
Re: [Qemu-riscv] [Qemu-devel] [PATCH] SiFive RISC-V GPIO Device
,
Alistair Francis
,
17:36
Re: [Qemu-riscv] [Qemu-devel] [PATCH] SiFive RISC-V GPIO Device
,
Peter Maydell
,
16:50
Re: [Qemu-riscv] [Qemu-devel] [PATCH] SiFive RISC-V GPIO Device
,
Palmer Dabbelt
,
15:27
Re: [Qemu-riscv] [Qemu-devel] [PATCH] SiFive RISC-V GPIO Device
,
Thomas Huth
,
13:54
Re: [Qemu-riscv] [Qemu-devel] [PATCH] hw/riscv/sifive_clint.c: avoid integer overflow in timecmp write
,
Palmer Dabbelt
,
13:23
Re: [Qemu-riscv] [Qemu-devel] [PATCH] RISC-V: Fix pmpcfg register indexing
,
Palmer Dabbelt
,
13:23
Re: [Qemu-riscv] [Qemu-devel] [PATCH] SiFive RISC-V GPIO Device
,
Peter Maydell
,
12:14
Re: [Qemu-riscv] [Qemu-devel] [PATCH] SiFive RISC-V GPIO Device
,
Fabien Chouteau
,
11:50
Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 01/35] target/riscv: Move CPURISCVState pointer to DisasContext
,
Bastian Koppelmann
,
11:18
[Qemu-riscv] [PATCH v7 33/35] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
,
Palmer Dabbelt
,
10:56
[Qemu-riscv] [PATCH v7 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions
,
Palmer Dabbelt
,
10:56
[Qemu-riscv] [PATCH v7 18/35] target/riscv: Convert quadrant 1 of RVXC insns to decodetree
,
Palmer Dabbelt
,
10:56
[Qemu-riscv] [PATCH v7 14/35] target/riscv: Convert RV32D insns to decodetree
,
Palmer Dabbelt
,
10:56
[Qemu-riscv] [PATCH v7 27/35] target/riscv: Remove manual decoding of RV32/64M insn
,
Palmer Dabbelt
,
10:56
[Qemu-riscv] [PATCH v7 35/35] target/riscv: Remaining rvc insn reuse 32 bit translators
,
Palmer Dabbelt
,
10:56
[Qemu-riscv] [PATCH v7 31/35] target/riscv: Convert @cs_2 insns to share translation functions
,
Palmer Dabbelt
,
10:56
[Qemu-riscv] [PATCH v7 16/35] target/riscv: Convert RV priv insns to decodetree
,
Palmer Dabbelt
,
10:56
[Qemu-riscv] [PATCH v7 34/35] target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
,
Palmer Dabbelt
,
10:56
[Qemu-riscv] [PATCH v7 30/35] target/riscv: Remove decode_RV32_64G()
,
Palmer Dabbelt
,
10:56
[Qemu-riscv] [PATCH v7 28/35] target/riscv: Rename trans_arith to gen_arith
,
Palmer Dabbelt
,
10:56
[Qemu-riscv] [PATCH v7 01/35] target/riscv: Move CPURISCVState pointer to DisasContext
,
Palmer Dabbelt
,
10:56
[Qemu-riscv] [PATCH v7 12/35] target/riscv: Convert RV32F insns to decodetree
,
Palmer Dabbelt
,
10:56
[Qemu-riscv] [PATCH v7 26/35] target/riscv: Remove shift and slt insn manual decoding
,
Palmer Dabbelt
,
10:56
[Qemu-riscv] [PATCH v7 32/35] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
,
Palmer Dabbelt
,
10:56
[Qemu-riscv] [PATCH v7 15/35] target/riscv: Convert RV64D insns to decodetree
,
Palmer Dabbelt
,
10:56
[Qemu-riscv] [PATCH v7 21/35] target/riscv: Remove manual decoding from gen_branch()
,
Palmer Dabbelt
,
10:56
[Qemu-riscv] [PATCH v7 22/35] target/riscv: Remove manual decoding from gen_load()
,
Palmer Dabbelt
,
10:56
[Qemu-riscv] [PATCH v7 23/35] target/riscv: Remove manual decoding from gen_store()
,
Palmer Dabbelt
,
10:56
[Qemu-riscv] [PATCH v7 00/35] target/riscv: Convert to decodetree
,
Palmer Dabbelt
,
10:56
[Qemu-riscv] [PATCH v7 05/35] target/riscv: Convert RV64I load/store insns to decodetree
,
Palmer Dabbelt
,
10:56
[Qemu-riscv] [PATCH v7 02/35] target/riscv: Activate decodetree and implemnt LUI & AUIPC
,
Palmer Dabbelt
,
10:56
[Qemu-riscv] [PATCH v7 25/35] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
,
Palmer Dabbelt
,
10:56
[Qemu-riscv] [PATCH v7 09/35] target/riscv: Convert RVXM insns to decodetree
,
Palmer Dabbelt
,
10:56
[Qemu-riscv] [PATCH v7 03/35] target/riscv: Convert RVXI branch insns to decodetree
,
Palmer Dabbelt
,
10:56
[Qemu-riscv] [PATCH v7 07/35] target/riscv: Convert RVXI fence insns to decodetree
,
Palmer Dabbelt
,
10:56
[Qemu-riscv] [PATCH v7 29/35] target/riscv: Remove gen_system()
,
Palmer Dabbelt
,
10:56
[Qemu-riscv] [PATCH v7 13/35] target/riscv: Convert RV64F insns to decodetree
,
Palmer Dabbelt
,
10:56
[Qemu-riscv] [PATCH v7 11/35] target/riscv: Convert RV64A insns to decodetree
,
Palmer Dabbelt
,
10:55
[Qemu-riscv] [PATCH v7 19/35] target/riscv: Convert quadrant 2 of RVXC insns to decodetree
,
Palmer Dabbelt
,
10:55
[Qemu-riscv] [PATCH v7 06/35] target/riscv: Convert RVXI arithmetic insns to decodetree
,
Palmer Dabbelt
,
10:55
[Qemu-riscv] [PATCH v7 20/35] target/riscv: Remove gen_jalr()
,
Palmer Dabbelt
,
10:55
[Qemu-riscv] [PATCH v7 17/35] target/riscv: Convert quadrant 0 of RVXC insns to decodetree
,
Palmer Dabbelt
,
10:55
[Qemu-riscv] [PATCH v7 10/35] target/riscv: Convert RV32A insns to decodetree
,
Palmer Dabbelt
,
10:55
[Qemu-riscv] [PATCH v7 08/35] target/riscv: Convert RVXI csr insns to decodetree
,
Palmer Dabbelt
,
10:55
[Qemu-riscv] [PATCH v7 04/35] target/riscv: Convert RV32I load/store insns to decodetree
,
Palmer Dabbelt
,
10:55
[Qemu-riscv] [PULL 07/11] RISC-V: Add misa.MAFD checks to translate
,
Palmer Dabbelt
,
10:45
[Qemu-riscv] [PULL 06/11] RISC-V: Add misa to DisasContext
,
Palmer Dabbelt
,
10:45
[Qemu-riscv] [PULL 03/11] RISC-V: Implement mstatus.TSR/TW/TVM
,
Palmer Dabbelt
,
10:45
[Qemu-riscv] [PULL 10/11] target/riscv: fix counter-enable checks in ctr()
,
Palmer Dabbelt
,
10:45
[Qemu-riscv] [PULL] RISC-V Patches for the 4.0 Soft Freeze, Part 1
,
Palmer Dabbelt
,
10:45
[Qemu-riscv] [PULL 08/11] RISC-V: Add misa runtime write support
,
Palmer Dabbelt
,
10:45
[Qemu-riscv] [PULL 09/11] MAINTAINERS: Remove Michael Clark as a RISC-V Maintainer
,
Palmer Dabbelt
,
10:45
[Qemu-riscv] [PULL 11/11] riscv: Ensure the kernel start address is correctly cast
,
Palmer Dabbelt
,
10:45
[Qemu-riscv] [PULL 05/11] RISC-V: Add priv_ver to DisasContext
,
Palmer Dabbelt
,
10:45
[Qemu-riscv] [PULL 04/11] RISC-V: Use riscv prefix consistently on cpu helpers
,
Palmer Dabbelt
,
10:45
[Qemu-riscv] [PULL 01/11] RISC-V: Split out mstatus_fs from tb_flags
,
Palmer Dabbelt
,
10:45
[Qemu-riscv] [PULL 02/11] RISC-V: Mark mstatus.fs dirty
,
Palmer Dabbelt
,
10:45
Re: [Qemu-riscv] [Qemu-devel] [PATCH v6 00/35] target/riscv: Convert to decodetree
,
Palmer Dabbelt
,
10:34
Re: [Qemu-riscv] [Qemu-devel] [PATCH v6 00/35] target/riscv: Convert to decodetree
,
Bastian Koppelmann
,
04:07
February 12, 2019
Re: [Qemu-riscv] [PATCH v6 00/35] target/riscv: Convert to decodetree
,
Palmer Dabbelt
,
21:15
Re: [Qemu-riscv] [Qemu-devel] [PATCH] SiFive RISC-V GPIO Device
,
Alistair Francis
,
19:07
Re: [Qemu-riscv] [Qemu-devel] [PATCH v4 5/5] RISC-V: Add hooks to use the gdb xml files.
,
Alistair Francis
,
18:26
Re: [Qemu-riscv] [PATCH v6 00/35] target/riscv: Convert to decodetree
,
Palmer Dabbelt
,
18:22
[Qemu-riscv] [PATCH v4 5/5] RISC-V: Add hooks to use the gdb xml files.
,
Jim Wilson
,
18:10
[Qemu-riscv] [PATCH v4 4/5] RISC-V: Add debug support for accessing CSRs.
,
Jim Wilson
,
18:09
[Qemu-riscv] [PATCH v4 3/5] RISC-V: Fixes to CSR_* register macros.
,
Jim Wilson
,
18:08
[Qemu-riscv] [PATCH v4 2/5] RISC-V: Add 64-bit gdb xml files.
,
Jim Wilson
,
18:08
[Qemu-riscv] [PATCH v4 1/5] RISC-V: Add 32-bit gdb xml files.
,
Jim Wilson
,
18:08
[Qemu-riscv] [PATCH v4 0/5] RISC-V: Add gdb xml files and gdbstub support.
,
Jim Wilson
,
18:05
[Qemu-riscv] [PATCH] SiFive RISC-V GPIO Device
,
Fabien Chouteau
,
12:39
February 11, 2019
Re: [Qemu-riscv] [Qemu-devel] [PATCH] hw/riscv/virt: re-add machine-specific compatible string to /soc/ node
,
Alistair Francis
,
18:48
Re: [Qemu-riscv] [Qemu-devel] [PATCH 5/5 v3] RISC-V: Add hooks to use the gdb xml files.
,
Palmer Dabbelt
,
13:17
February 10, 2019
[Qemu-riscv] [PATCH] hw/riscv/virt: re-add machine-specific compatible string to /soc/ node
,
Lukas Auer
,
15:21
February 08, 2019
[Qemu-riscv] [PATCH v1 11/11] RISC-V: Update load reservation comment in do_interrupt
,
Alistair Francis
,
20:01
[Qemu-riscv] [PATCH v1 10/11] RISC-V: Convert trap debugging to trace events
,
Alistair Francis
,
20:01
[Qemu-riscv] [PATCH v1 09/11] RISC-V: Add support for vectored interrupts
,
Alistair Francis
,
20:01
[Qemu-riscv] [PATCH v1 08/11] RISC-V: Change local interrupts from edge to level
,
Alistair Francis
,
20:01
[Qemu-riscv] [PATCH v1 07/11] RISC-V: linux-user support for RVE ABI
,
Alistair Francis
,
20:00
[Qemu-riscv] [PATCH v1 06/11] elf: Add RISC-V PSABI ELF header defines
,
Alistair Francis
,
20:00
[Qemu-riscv] [PATCH v1 05/11] RISC-V: Remove unnecessary disassembler constraints
,
Alistair Francis
,
20:00
[Qemu-riscv] [PATCH v1 04/11] RISC-V: Allow interrupt controllers to claim interrupts
,
Alistair Francis
,
20:00
[Qemu-riscv] [PATCH v1 03/11] RISC-V: Replace __builtin_popcount with ctpop8 in PLIC
,
Alistair Francis
,
19:59
[Qemu-riscv] [PATCH v1 02/11] riscv: pmp: Log pmp access errors as guest errors
,
Alistair Francis
,
19:59
[Qemu-riscv] [PATCH v1 01/11] riscv: Ensure the kernel start address is correctly cast
,
Alistair Francis
,
19:59
[Qemu-riscv] [PATCH v1 00/11] Upstream RISC-V fork patches, part 4
,
Alistair Francis
,
19:59
Re: [Qemu-riscv] [Qemu-devel] [PATCH] RISC-V: Fix pmpcfg register indexing
,
Alistair Francis
,
15:56
Re: [Qemu-riscv] [Qemu-devel] [PATCH 5/5 v3] RISC-V: Add hooks to use the gdb xml files.
,
Jim Wilson
,
15:48
Re: [Qemu-riscv] [Qemu-devel] [PATCH 5/5 v3] RISC-V: Add hooks to use the gdb xml files.
,
Alistair Francis
,
15:45
Re: [Qemu-riscv] [Qemu-devel] [PATCH 5/5 v3] RISC-V: Add hooks to use the gdb xml files.
,
Alistair Francis
,
15:45
Re: [Qemu-riscv] [Qemu-devel] [PATCH] hw/riscv/sifive_clint.c: avoid integer overflow in timecmp write
,
Alistair Francis
,
15:22
February 07, 2019
Re: [Qemu-riscv] [Qemu-devel] [PATCH 5/5 v3] RISC-V: Add hooks to use the gdb xml files.
,
Richard Henderson
,
07:04
Re: [Qemu-riscv] [Qemu-devel] [PATCH] hw/riscv/sifive_clint.c: avoid integer overflow in timecmp write
,
Fabien Chouteau
,
05:08
February 06, 2019
Re: [Qemu-riscv] [Qemu-devel] [PATCH 5/5 v3] RISC-V: Add hooks to use the gdb xml files.
,
Jim Wilson
,
21:05
Re: [Qemu-riscv] [Qemu-devel] [PATCH] hw/riscv/sifive_clint.c: avoid integer overflow in timecmp write
,
Alistair Francis
,
19:43
Re: [Qemu-riscv] [Qemu-devel] [PATCH 5/5 v3] RISC-V: Add hooks to use the gdb xml files.
,
Alistair Francis
,
19:05
Re: [Qemu-riscv] [Qemu-devel] [PATCH 4/5 v3] RISC-V: Add debug support for accessing CSRs.
,
Alistair Francis
,
18:56
Re: [Qemu-riscv] [Qemu-devel] [PATCH 3/5 v3] RISC-V: Fixes to CSR_* register macros.
,
Alistair Francis
,
18:55
Re: [Qemu-riscv] [Qemu-devel] [PATCH 2/5 v3] RISC-V: Add 64-bit gdb xml files.
,
Alistair Francis
,
18:54
Re: [Qemu-riscv] [Qemu-devel] [PATCH 1/5 v3] RISC-V: Add 32-bit gdb xml files.
,
Alistair Francis
,
18:53
Re: [Qemu-riscv] [Qemu-devel] [PR RFC] RISC-V Patches for 3.2, Part 3
,
Palmer Dabbelt
,
11:48
February 05, 2019
Re: [Qemu-riscv] [Qemu-devel] [Bug 1814343] [NEW] Initrd not loaded on riscv32
,
Alistair Francis
,
13:37
Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 3/3] util/cutils: Move function documentations to the header
,
Daniel P . Berrangé
,
08:54
Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 2/3] util/cutils: Move ctype macros to "cutils.h"
,
Daniel P . Berrangé
,
08:54
Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 3/3] util/cutils: Move function documentations to the header
,
Markus Armbruster
,
07:31
Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 3/3] util/cutils: Move function documentations to the header
,
Peter Maydell
,
05:57
Re: [Qemu-riscv] [PATCH v3 2/3] util/cutils: Move ctype macros to "cutils.h"
,
Cornelia Huck
,
05:40
Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 3/3] util/cutils: Move function documentations to the header
,
Markus Armbruster
,
01:43
February 04, 2019
[Qemu-riscv] [PATCH v3 2/3] util/cutils: Move ctype macros to "cutils.h"
,
Philippe Mathieu-Daudé
,
16:18
[Qemu-riscv] [PATCH v3 3/3] util/cutils: Move function documentations to the header
,
Philippe Mathieu-Daudé
,
16:13
[Qemu-riscv] [PATCH v3 1/3] util/cutils: Move size_to_str() from "qemu-common.h" to "cutils.h"
,
Philippe Mathieu-Daudé
,
16:12
[Qemu-riscv] [PATCH v3 0/3] cutils: Cleanup, improve documentation
,
Philippe Mathieu-Daudé
,
16:12
Re: [Qemu-riscv] [Qemu-devel] [PR RFC] RISC-V Patches for 3.2, Part 3
,
Peter Maydell
,
05:00
Re: [Qemu-riscv] [Qemu-devel] [PR RFC] RISC-V Patches for 3.2, Part 3
,
Thomas Huth
,
04:05
February 02, 2019
[Qemu-riscv] [PULL] RISC-V Patches for 3.2, Part 3
,
Palmer Dabbelt
,
04:53
[Qemu-riscv] [PULL 02/10] RISC-V: Mark mstatus.fs dirty
,
Palmer Dabbelt
,
04:53
[Qemu-riscv] [PULL 04/10] RISC-V: Use riscv prefix consistently on cpu helpers
,
Palmer Dabbelt
,
04:53
[Qemu-riscv] [PULL 03/10] RISC-V: Implement mstatus.TSR/TW/TVM
,
Palmer Dabbelt
,
04:53
[Qemu-riscv] [PULL 10/10] target/riscv: fix counter-enable checks in ctr()
,
Palmer Dabbelt
,
04:53
[Qemu-riscv] [PULL 05/10] RISC-V: Add priv_ver to DisasContext
,
Palmer Dabbelt
,
04:53
[Qemu-riscv] [PULL 06/10] RISC-V: Add misa to DisasContext
,
Palmer Dabbelt
,
04:53
[Qemu-riscv] [PULL 08/10] RISC-V: Add misa runtime write support
,
Palmer Dabbelt
,
04:53
[Qemu-riscv] [PULL 07/10] RISC-V: Add misa.MAFD checks to translate
,
Palmer Dabbelt
,
04:53
[Qemu-riscv] [PULL 01/10] RISC-V: Split out mstatus_fs from tb_flags
,
Palmer Dabbelt
,
04:53
[Qemu-riscv] [PULL 09/10] MAINTAINERS: Remove Michael Clark as a RISC-V Maintainer
,
Palmer Dabbelt
,
04:53
Re: [Qemu-riscv] [Qemu-devel] [PR RFC] RISC-V Patches for 3.2, Part 3
,
Palmer Dabbelt
,
03:42
Re: [Qemu-riscv] [Qemu-devel] [PR RFC] RISC-V Patches for 3.2, Part 3
,
Palmer Dabbelt
,
03:42
February 01, 2019
Re: [Qemu-riscv] [Qemu-devel] [Bug 1814343] [NEW] Initrd not loaded on riscv32
,
Philippe Mathieu-Daudé
,
18:25
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
,
no-reply
,
05:35
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