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[Qemu-riscv] [PULL 29/32] riscv: sifive_u: Update the plic hart config t
From: |
Palmer Dabbelt |
Subject: |
[Qemu-riscv] [PULL 29/32] riscv: sifive_u: Update the plic hart config to support multicore |
Date: |
Wed, 3 Jul 2019 01:40:45 -0700 |
From: Bin Meng <address@hidden>
At present the PLIC is instantiated to support only one hart, while
the machine allows at most 4 harts to be created. When more than 1
hart is configured, PLIC needs to instantiated to support multicore,
otherwise an SMP OS does not work.
Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
hw/riscv/sifive_u.c | 16 +++++++++++++++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index e2120ac7a5d3..a416d5d08b4d 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -344,6 +344,8 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev,
Error **errp)
MemoryRegion *system_memory = get_system_memory();
MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
qemu_irq plic_gpios[SIFIVE_U_PLIC_NUM_SOURCES];
+ char *plic_hart_config;
+ size_t plic_hart_config_len;
int i;
Error *err = NULL;
NICInfo *nd = &nd_table[0];
@@ -357,9 +359,21 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev,
Error **errp)
memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base,
mask_rom);
+ /* create PLIC hart topology configuration string */
+ plic_hart_config_len = (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) * smp_cpus;
+ plic_hart_config = g_malloc0(plic_hart_config_len);
+ for (i = 0; i < smp_cpus; i++) {
+ if (i != 0) {
+ strncat(plic_hart_config, ",", plic_hart_config_len);
+ }
+ strncat(plic_hart_config, SIFIVE_U_PLIC_HART_CONFIG,
+ plic_hart_config_len);
+ plic_hart_config_len -= (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1);
+ }
+
/* MMIO */
s->plic = sifive_plic_create(memmap[SIFIVE_U_PLIC].base,
- (char *)SIFIVE_U_PLIC_HART_CONFIG,
+ plic_hart_config,
SIFIVE_U_PLIC_NUM_SOURCES,
SIFIVE_U_PLIC_NUM_PRIORITIES,
SIFIVE_U_PLIC_PRIORITY_BASE,
--
2.21.0
- [Qemu-riscv] [PULL 20/32] target/riscv: Add support for disabling/enabling Counters, (continued)
- [Qemu-riscv] [PULL 20/32] target/riscv: Add support for disabling/enabling Counters, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 24/32] RISC-V: Update syscall list for 32-bit support., Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 19/32] target/riscv: Remove user version information, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 21/32] RISC-V: Add support for the Zifencei extension, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 23/32] RISC-V: Clear load reservations on context switch and SC, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 28/32] riscv: sifive_u: Do not create hard-coded phandles in DT, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 32/32] hw/riscv: Extend the kernel loading support, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 26/32] disas/riscv: Disassemble reserved compressed encodings as illegal, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 31/32] hw/riscv: Add support for loading a firmware, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 25/32] riscv: virt: Add cpu-topology DT node., Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 29/32] riscv: sifive_u: Update the plic hart config to support multicore,
Palmer Dabbelt <=
- [Qemu-riscv] [PULL 27/32] disas/riscv: Fix `rdinstreth` constraint, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 30/32] hw/riscv: Split out the boot functions, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 22/32] RISC-V: Add support for the Zicsr extension, Palmer Dabbelt, 2019/07/03
- Re: [Qemu-riscv] [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v3, Peter Maydell, 2019/07/04