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Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 13/15] cputlb: Byte swap memory
From: |
Richard Henderson |
Subject: |
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 13/15] cputlb: Byte swap memory transaction attribute |
Date: |
Fri, 26 Jul 2019 07:52:08 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 |
On 7/25/19 11:48 PM, address@hidden wrote:
> Notice new attribute, byte swap, and force the transaction through the
> memory slow path.
>
> Required by architectures that can invert endianness of memory
> transaction, e.g. SPARC64 has the Invert Endian TTE bit.
>
> Signed-off-by: Tony Nguyen <address@hidden>
> ---
> accel/tcg/cputlb.c | 11 +++++++++++
> include/exec/memattrs.h | 2 ++
> 2 files changed, 13 insertions(+)
>
> diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
> index e61b1eb..f292a87 100644
> --- a/accel/tcg/cputlb.c
> +++ b/accel/tcg/cputlb.c
> @@ -738,6 +738,9 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong
> vaddr,
> */
> address |= TLB_RECHECK;
> }
> + if (attrs.byte_swap) {
> + address |= TLB_FORCE_SLOW;
> + }
> if (!memory_region_is_ram(section->mr) &&
> !memory_region_is_romd(section->mr)) {
> /* IO memory case */
> @@ -891,6 +894,10 @@ static uint64_t io_readx(CPUArchState *env,
> CPUIOTLBEntry *iotlbentry,
> bool locked = false;
> MemTxResult r;
>
> + if (iotlbentry->attrs.byte_swap) {
> + op ^= MO_BSWAP;
> + }
> +
> section = iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs);
> mr = section->mr;
> mr_offset = (iotlbentry->addr & TARGET_PAGE_MASK) + addr;
> @@ -933,6 +940,10 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry
> *iotlbentry,
> bool locked = false;
> MemTxResult r;
>
> + if (iotlbentry->attrs.byte_swap) {
> + op ^= MO_BSWAP;
> + }
> +
> section = iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs);
> mr = section->mr;
> mr_offset = (iotlbentry->addr & TARGET_PAGE_MASK) + addr;
> diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h
> index d4a3477..a0644eb 100644
> --- a/include/exec/memattrs.h
> +++ b/include/exec/memattrs.h
> @@ -37,6 +37,8 @@ typedef struct MemTxAttrs {
> unsigned int user:1;
> /* Requester ID (for MSI for example) */
> unsigned int requester_id:16;
> + /* SPARC64: TTE invert endianness */
> + unsigned int byte_swap:1;
Don't mention Sparc here, otherwise it seems like it only applies to Sparc,
when it is really a generic feature only currently used by Sparc.
Just say "Invert endianness for this page".
With that,
Reviewed-by: Richard Henderson <address@hidden>
r~
- [Qemu-riscv] [Qemu-devel] [PATCH v5 10/15] memory: Access MemoryRegion with MemOp semantics, (continued)
- [Qemu-riscv] [Qemu-devel] [PATCH v5 10/15] memory: Access MemoryRegion with MemOp semantics, tony.nguyen, 2019/07/26
- [Qemu-riscv] [Qemu-devel] [PATCH v5 11/15] memory: Single byte swap along the I/O path, tony.nguyen, 2019/07/26
- [Qemu-riscv] [Qemu-devel] [PATCH v5 12/15] cpu: TLB_FLAGS_MASK bit to force memory slow path, tony.nguyen, 2019/07/26
- [Qemu-riscv] [Qemu-devel] [PATCH v5 13/15] cputlb: Byte swap memory transaction attribute, tony.nguyen, 2019/07/26
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 13/15] cputlb: Byte swap memory transaction attribute,
Richard Henderson <=
- [Qemu-riscv] [Qemu-devel] [PATCH v5 14/15] target/sparc: Add TLB entry with attributes, tony.nguyen, 2019/07/26
- [Qemu-riscv] [Qemu-devel] [PATCH v5 15/15] target/sparc: sun4u Invert Endian TTE bit, tony.nguyen, 2019/07/26